Design of Power-efficient Analog-to-digital Converters and a Mixed-mode low Drop-out Regulator

The increasing demand of portable electronic devices, such as cell phones, biomedical products, smart devices, etc, has been witnessed in recent years. These devices have limited power due to their battery life. Therefore, power-efficient researches and designs for IC chips used in the portable devices become more popular. One hot topic is about a power-efficient high resolution, wide bandwidth analog-to-digital converter (ADC) design. The ADC block is one of the key building blocks in a wireless communication system. The ADC is employed to process baseband signals after a mixer and filters. It converts analog signals into digital format for microprocessors/controllers. Hence, the power consumption of the ADC is important since the ADC is one of the most frequently used building blocks in the wireless communication system. Another widely used blocks are on-chip regulators. They regulate the supply voltages for different parts/cores on a microchip. Nowadays, many applications require different building blocks switching frequently between sleeping and operation modes. In this case, power-efficient on-chip regulators with fast transient response are demanded. This research consists of three projects. All projects are about power-efficient analog and mixed-signal circuits design. The first research is a 13-bit 260MS/s pipeline ADC using a currentmode (CM) multiplying digital-to-analog converter (MDAC) with a current-reuse technique and interstage gain calibrations. In this pipeline ADC, the CM MDAC architecture is utilized to replace the conventional switch-capacitor (SC) architecture. The CM MDAC employs an operational transconductance amplifier (OTA) converting the voltage input signal into a current output signal. At the same time, the sub-ADC in the CM MDAC solves N bits which drives an N-bit currentsteering DAC. The current residue signal is generated at the output of the DAC and the OTA. Then, a transimpedance amplifier (TIA) is utilized to convert the current residue back to a voltage output for next pipeline stages. To overcome interstage gain errors due to variations, the errors are calibrated in digital domain. Finally, the work achieves a 68.1/66.3 dB signal-to-noise-anddistortion ratio (SNDR) and 82.3/78.2 dB spurious free dynamic range (SFDR) for a sinusoidal inputs at 4.1736/123.129 MHz. The total power consumption for the ADC is around 15.38 mW. The Walden figure-of-merit (FoM) is 28.3 fJ/conv-step with low frequency input. The chip was implemented by TSMC 40nm technology. The phototype occupies around 0.28 mm2 . The second project is a system-level design of a time-interleaved ADC with digital background calibrations. In this project, a 4-channel time-interleaved ADC with one additional ADC for calibration is proposed. The calibration algorithm matches the 4-channel ADCs’ outputs with the additional ADC by adjusting their gains, offsets and sampling clock phases. These three types of mismatches and skews are considered as the main errors for a high-speed time-interleaved architecture. The algorithm is implemented and functionally verified by using a field programmable gate array (FPGA) and commercial ADCs (ADS4126). In the last project, a 245mA digitally-assisted dual-loop low dropout (LDO) regulator is proposed and implemented in a TSMC40nm process. The purposed digitally-assisted loop is to speed up the transient response of large load variations. In this way, the digital loop maintains the loop speed of the LDO using dynamic current instead of large DC current. However, the digital loop has finite resolution leading to a current quantization error at the output. One of pass transistors in the LDO is turned on/off periodically in a steady state condition. In order to solve the issue, the analog loop is utilized for the steady state condition. It regulates small load changes. The digital loop is activated for tracking large load steps only. The digitally-assisted dual-loop LDO achieves 245mA maximum load current. The power supply rejection (PSR) is -48 dB at low frequency and -43 dB at 1 MHz for a 240 mA load respectively. The LDO with low load current still shows -34 dB rejection at 1 MHz. The quiescent current is approximate to 300 µA. The measured load transient tests indicate that the LDO has 71 mV/37 mV voltage droops under a rising/falling edge of the maximum current step. The FoM based on the results is 7.4 ps which is highly competitive with recently published LDO designs

Design of Power-efficient Analog-to-digital Converters and a Mixed-mode low Drop-out Regulator

The increasing demand of portable electronic devices, such as cell phones, biomedical products, smart devices, etc, has been witnessed in recent years. These devices have limited power due to their battery life. Therefore, power-efficient researches and designs for IC chips used in the portable devices become more popular. One hot topic is about a power-efficient high resolution, wide bandwidth analog-to-digital converter (ADC) design. The ADC block is one of the key building blocks in a wireless communication system. The ADC is employed to process baseband signals after a mixer and filters. It converts analog signals into digital format for microprocessors/controllers. Hence, the power consumption of the ADC is important since the ADC is one of the most frequently used building blocks in the wireless communication system. Another widely used blocks are on-chip regulators. They regulate the supply voltages for different parts/cores on a microchip. Nowadays, many applications require different building blocks switching frequently between sleeping and operation modes. In this case, power-efficient on-chip regulators with fast transient response are demanded. This research consists of three projects. All projects are about power-efficient analog and mixed-signal circuits design. The first research is a 13-bit 260MS/s pipeline ADC using a currentmode (CM) multiplying digital-to-analog converter (MDAC) with a current-reuse technique and interstage gain calibrations. In this pipeline ADC, the CM MDAC architecture is utilized to replace the conventional switch-capacitor (SC) architecture. The CM MDAC employs an operational transconductance amplifier (OTA) converting the voltage input signal into a current output signal. At the same time, the sub-ADC in the CM MDAC solves N bits which drives an N-bit currentsteering DAC. The current residue signal is generated at the output of the DAC and the OTA. Then, a transimpedance amplifier (TIA) is utilized to convert the current residue back to a voltage output for next pipeline stages. To overcome interstage gain errors due to variations, the errors are calibrated in digital domain. Finally, the work achieves a 68.1/66.3 dB signal-to-noise-anddistortion ratio (SNDR) and 82.3/78.2 dB spurious free dynamic range (SFDR) for a sinusoidal inputs at 4.1736/123.129 MHz. The total power consumption for the ADC is around 15.38 mW. The Walden figure-of-merit (FoM) is 28.3 fJ/conv-step with low frequency input. The chip was implemented by TSMC 40nm technology. The phototype occupies around 0.28 mm2 . The second project is a system-level design of a time-interleaved ADC with digital background calibrations. In this project, a 4-channel time-interleaved ADC with one additional ADC for calibration is proposed. The calibration algorithm matches the 4-channel ADCs’ outputs with the additional ADC by adjusting their gains, offsets and sampling clock phases. These three types of mismatches and skews are considered as the main errors for a high-speed time-interleaved architecture. The algorithm is implemented and functionally verified by using a field programmable gate array (FPGA) and commercial ADCs (ADS4126). In the last project, a 245mA digitally-assisted dual-loop low dropout (LDO) regulator is proposed and implemented in a TSMC40nm process. The purposed digitally-assisted loop is to speed up the transient response of large load variations. In this way, the digital loop maintains the loop speed of the LDO using dynamic current instead of large DC current. However, the digital loop has finite resolution leading to a current quantization error at the output. One of pass transistors in the LDO is turned on/off periodically in a steady state condition. In order to solve the issue, the analog loop is utilized for the steady state condition. It regulates small load changes. The digital loop is activated for tracking large load steps only. The digitally-assisted dual-loop LDO achieves 245mA maximum load current. The power supply rejection (PSR) is -48 dB at low frequency and -43 dB at 1 MHz for a 240 mA load respectively. The LDO with low load current still shows -34 dB rejection at 1 MHz. The quiescent current is approximate to 300 µA. The measured load transient tests indicate that the LDO has 71 mV/37 mV voltage droops under a rising/falling edge of the maximum current step. The FoM based on the results is 7.4 ps which is highly competitive with recently published LDO designs

Enhancing the Local Search Ability of the Brain Storm Optimization Algorithm by Covariance Matrix Adaptation

Recently, the Brain Storm Optimization (BSO) algorithm has attracted many researchers and practitioners attention from the evolutionary computation community. However, like many other population based algorithms, BSO shows good performance at global exploration but not good enough at local exploitation. To alleviate this issue, in this chapter, the Covariance Matrix Adaptation Evolution Strategy (CMA-ES) is utilized in the Global-best BSO (GBSO), with the aim to combine the exploration ability of BSO and local ability of CMA-ES and to design an improved version of BSO. The performance of the proposed algorithm is tested by solving 28 classical optimization problems and the proposed algorithm is shown to perform better than GBSO.</p

The Society for Vascular Surgery practice guidelines on the care of patients with an abdominal aortic aneurysm

BACKGROUND: Decision-making related to the care of patients with an abdominal aortic aneurysm (AAA) is complex. Aneurysms present with varying risks of rupture, and patient-specific factors influence anticipated life expectancy, operative risk, and need to intervene. Careful attention to the choice of operative strategy along with optimal treatment of medical comorbidities is critical to achieving excellent outcomes. Moreover, appropriate postoperative surveillance is necessary to minimize subsequent aneurysm-related death or morbidity. METHODS: The committee made specific practice recommendations using the Grading of Recommendations Assessment, Development, and Evaluation system. Three systematic reviews were conducted to support this guideline. Two focused on evaluating the best modalities and optimal frequency for surveillance after endovascular aneurysm repair (EVAR). A third focused on identifying the best available evidence on the diagnosis and management of AAA. Specific areas of focus included (1) general approach to the patient, (2) treatment of the patient with an AAA, (3) anesthetic considerations and perioperative management, (4) postoperative and long-term management, and (5) cost and economic considerations. RESULTS: Along with providing guidance regarding the management of patients throughout the continuum of care, we have revised a number of prior recommendations and addressed a number of new areas of significance. New guidelines are provided for the surveillance of patients with an AAA, including recommended surveillance imaging at 12-month intervals for patients with an AAA of 4.0 to 4.9 cm in diameter. We recommend endovascular repair as the preferred method of treatment for ruptured aneurysms. Incorporating knowledge gained through the Vascular Quality Initiative and other regional quality collaboratives, we suggest that the Vascular Quality Initiative mortality risk score be used for mutual decision-making with patients considering aneurysm repair. We also suggest that elective EVAR be limited to hospitals with a documented mortality and conversion rate to open surgical repair of 2% or less and that perform at least 10 EVAR cases each year. We also suggest that elective open aneurysm repair be limited to hospitals with a documented mortality of 5% or less and that perform at least 10 open aortic operations of any type each year. To encourage the development of effective systems of care that would lead to improved outcomes for those patients undergoing emergent repair, we suggest a door-to-intervention time of \u3c90 \u3eminutes, based on a framework of 30-30-30 minutes, for the management of the patient with a ruptured aneurysm. We recommend treatment of type I and III endoleaks as well as of type II endoleaks with aneurysm expansion but recommend continued surveillance of type II endoleaks not associated with aneurysm expansion. Whereas antibiotic prophylaxis is recommended for patients with an aortic prosthesis before any dental procedure involving the manipulation of the gingival or periapical region of teeth or perforation of the oral mucosa, antibiotic prophylaxis is not recommended before respiratory tract procedures, gastrointestinal or genitourinary procedures, and dermatologic or musculoskeletal procedures unless the potential for infection exists or the patient is immunocompromised. Increased utilization of color duplex ultrasound is suggested for postoperative surveillance after EVAR in the absence of endoleak or aneurysm expansion. CONCLUSIONS: Important new recommendations are provided for the care of patients with an AAA, including suggestions to improve mutual decision-making between the treating physician and the patients and their families as well as a number of new strategies to enhance perioperative outcomes for patients undergoing elective and emergent repair. Areas of uncertainty are highlighted that would benefit from further investigation in addition to existing limitations in diagnostic tests, pharmacologic agents, intraoperative tools, and devices