A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Low mass hybrid pixel detectors for the high luminosity LHC upgrade

Reducing material in silicon trackers is of major importance for a good overall detector performance, and poses severe challenges to the design of the tracking system. To match the low mass constraints for trackers in High Energy Physics experiments at high luminosity, dedicated technological developments are required. This dissertation presents three technologies to design low mass hybrid pixel detectors for the high luminosity upgrades of the LHC. The work targets specifically the reduction of the material from the detector services and modules, with novel powering schemes, flip chip and interconnection technologies. A serial powering scheme is prototyped, featuring a new regulator concept, a control and protection element, and AC-coupled data transmission. A modified flip chip technology is developed for thin, large area Front-End chips, and a via last Through Silicon Via process is demonstrated on existing pixel modules. These technologies, their developments, and the achievable material reduction are discussed using the upgrades of the ATLAS pixel detector as a case study

Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium

The articles in this special section were presented at the 2019 IEEE VLSI Test Symposium (VTS) that was held in Monterey, CA. The 2019 VTS Conference laid particular emphasis on enlarging its scope by soliciting submissions on testing, reliability, and security aspects on the following hot topics: approximate computing, neuromorphic computing, and quantum computing

Through Silicon Via의 Coupling Noise를 억제하는 반전 전하층을 이용한 Guard Ring 제작 및 분석

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 8. 이종호.As technology shrinks, the implementation of high-density chip with a two-dimensional (2-D) planar architecture is becoming more difficult due to the limitation of lithography process. To overcome such scale-down limitations, a three-dimensional (3-D) package has been investigated. Among the various 3-D package technologies, a through silicon via (TSV) is a promising technology in which several chips are stacked vertically and electrically. This 3-D package can enhance the memory capacity, and implement a system with different functional chips. Although TSVs offer many advantages when used to achieve a high-density package, they also have several disadvantages, such as coupling noise. A high-frequency signal applied to a TSV induces noise in transistors near the TSV due to electrical coupling. Another issue is that copper (Cu) which is used as a conducting material of the TSV generates trap density caused by large diffusivity of Cu atoms. In this dissertation, we propose a new guard ring which consists of a shallow n+ region, a deep n-well, and an inversion layer formed along the interface between the oxide surrounding the TSV (TSV oxide) and the p-substrate. The proposed guard ring utilizes an inversion charge induced by a positive oxide charge located at the interface of the TSV oxide. We characterize quantitatively a TSV with a guard ring which is used to reduce the coupling noise from the TSV by utilizing an inversion layer as a shield layer. It is shown that a transient current due to the coupling is clearly reduced when the proposed guard ring is used. The proposed method is compared with a conventional guard ring method in terms of the drain current of a victim nMOSFET. The effective depth of the inversion layer with the signal frequency is also characterized. It is demonstrated that the high-frequency response of the guard ring can be modeled as an RC equivalent circuit. The proposed guard ring is effective in shielding the coupling noise and can be fabricated easily by modifying the ion implantation mask layer. A TSV conducting material requires high conductivity for low power consumption and high-speed operation. Cu is widely used as a TSV conducting material, but Cu atoms diffuse to the adjacent silicon substrate and transistors easily and generate traps during a low temperature annealing process. It is very important to suppress Cu diffusion and to devise a proper method to measure how many Cu atoms diffuse due to annealing. However, the characteristics of traps induced by Cu diffusion in a TSV are not easily measured because TSVs are typically located some distance away from the silicon surface, reaching a depth of tens of micrometers. For this reason, the deep part of a TSV cannot be measured. We suggest a measurement method which can be used to evaluate the trap density generated by Cu diffusion through the use of the proposed guard ring and analyze Cu diffusion as a parameter of the thickness of the barrier metal.Contents Abstract 1 Contents 4 Chapter 1 Introduction 6 1.1 BACKGROUND OF TSV 6 1.2 MOTIVATION FOR THE RESEARCH 14 Chapter 2 Structure of the guard ring and the TSV 15 2.1 INTRODUCTION 15 2.2 PROCESS FLOW OF FABRICATING TSV AND GUARD RING 20 2.3 STRUCTURE OF THE TSV AND THE PROPOSED GUARD RING 24 Chapter 3 Characteristics of the proposed guard ring 27 3.1 INTRODUCTION 27 3.2 JUNCTION CHARACTERISTICS OF THE PROPOSED GUARD RING 28 3.3 C-V CHARACTERISTICS OF THE PROPOSED GUARD RING 31 Chapter 4 Effective method to analyze the trap density 40 4.1 INTRODUCTION 40 4.2 CHARACTERISTICS OF CU DIFFUSION WITH BARRIER METAL THICKNESS 42 4.3 EFFECT OF CU DIFFUSION ENHANCED BY ADDITIONAL ANNEALING 53 Chapter 5 Shielding ability of the proposed guard ring 65 5.1 INTRODUCTION 65 5.2 SHIELDING ABILITY OF THE PROPOSED GUARD RING 69 5.3 EFFECTIVENESS OF THE PROPOSED GUARD RING 75 5.4 CHARACTERISTICS OF THE PROPOSED GUARD RING BY RC MODELING 86 Conclusions 91 Bibliography 93 Abstract in Korean 98Docto

INVESTIGATION OF TECHNIQUES FOR REDUCING UNINTENTIONAL ELECTROMAGNETIC EMISSIONS FROM ELECTRONIC CIRCUITS AND SYSTEMS

This dissertation describes three independent studies related to techniques for reducing unintentional electromagnetic emissions from electronic circuits and systems. The topics covered are: low-inductance multi-layer ceramic capacitor for high frequency circuit board decoupling, the application of imbalance difference model to various circuit board and cable geometries, and balanced cable interface for reducing common-mode currents from power inverter. The first chapter discusses the importance and the meaning of the connection inductance associated with MLCCs and analyzes the effect of plate orientation in MLCCs. It demonstrates that vertically oriented plates have no more or less inductance than horizontally oriented plates when the overall dimensions of the plate stack are similar. Decoupling capacitance options at the various levels of a high-speed circuit is investigated to determine the range of frequencies that decoupling at each level is likely to be is effective. Innovative low-inductance capacitive-stem capacitor configurations are described and their connection impedance is compared to that of standard surface-mounted capacitors. The second chapter investigates the imbalance difference model that is a method for modeling how differential-mode signal currents are converted to common-mode noise currents. Various cable geometries to determine how well imbalance factor`s values of DM-to-CM conversion compare to full-wave calculations are explored. The imbalance difference model can be applied to cables with more than two conductors are demonstrated. The third chapter investigates the balanced cable interface for reducing common-mode currents from power inverter. The concept of a balancing network to reduce the common-mode currents on power inverter cables above 30 MHz is introduced. An experimental test set-up is used to demonstrate the effect of a balancing network on the common-mode current, differential-mode current and the common-mode rejection ratio on a balanced cable with an imbalanced termination. The balancing network is also evaluated using a 3-phase brushless DC motor driver to verify its effectiveness in a real application

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Parallel vs. Serial Inter-plane communication using TSVs

3-D integration is a promising prospect for implementing high performance multifunctional systems-on- chip. Through Silicon Vias (TSVs) are the enablers for achieving high bandwidth paths in inter-plane communications. TSVs also provide higher vertical link density and facilitate the heat flow in the 3-D circuits as compared to other potential schemes such as inductive links. However, reliability issues and crosstalk problems among adjacent TSVs decrease the yield and performance of TSV based circuits. Reducing the number of TSVs employed for inter-plane signal transferring can alleviate these problems. This paper proposes to exploit serialization to reduce the number of TSVs in a 3D circuit and presents a comparison between different aspects of TSV-based 3-D circuits such as area, power, crosstalk and yield in parallel and serial vertical links

R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging

This report reviews current trends in the R&D of semiconductor pixellated sensors for vertex tracking and radiation imaging. It identifies requirements of future HEP experiments at colliders, needed technological breakthroughs and highlights the relation to radiation detection and imaging applications in other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory Grou