An Interpretable Systematic Review of Machine Learning Models for Predictive Maintenance of Aircraft Engine

This paper presents an interpretable review of various machine learning and deep learning models to predict the maintenance of aircraft engine to avoid any kind of disaster. One of the advantages of the strategy is that it can work with modest datasets. In this study, sensor data is utilized to predict aircraft engine failure within a predetermined number of cycles using LSTM, Bi-LSTM, RNN, Bi-RNN GRU, Random Forest, KNN, Naive Bayes, and Gradient Boosting. We explain how deep learning and machine learning can be used to generate predictions in predictive maintenance using a straightforward scenario with just one data source. We applied lime to the models to help us understand why machine learning models did not perform well than deep learning models. An extensive analysis of the model's behavior is presented for several test data to understand the black box scenario of the models. A lucrative accuracy of 97.8%, 97.14%, and 96.42% are achieved by GRU, Bi-LSTM, and LSTM respectively which denotes the capability of the models to predict maintenance at an early stage

Effect of probiotics and acidifiers on feed intake, egg mass, production performance, and egg yolk chemical composition in late-laying quails

Background and Aim: Probiotics can be used as an alternative to antibiotic growth promoters because antibiotics are prohibited worldwide. This study investigated the potential combination of probiotics and acidifiers to improve feed intake, productive performance, egg mass, and egg yolk chemical composition of late-laying quail for the health of humans who consume quail products. Materials and Methods: One hundred laying quails were divided into 4 × 5 treatments, with each group consisting of five replications. The adaptation period was 2 weeks, and the treatment was continued for 4 weeks. Probiotics and acidifiers were added to drinking water and incorporated into the diet. Feed and water were provided ad libitum. Treatment duration (1 week, 2 weeks, 3 weeks, and 4 weeks) and additional feed treatment (control, probiotic 2% + 0.5% acidifier, probiotic 2% + 1% acidifier, probiotic 4% + 0.5% acidifier, and probiotic 4% + 1% acidifier, respectively). Results: Significant differences (p < 0.05) were observed in feed intake, quail day production, feed efficiency, egg mass in laying quails, and the chemical composition of egg yolk with probiotics and acidifiers in late-laying quails. Conclusion: The combination of probiotics and acidifiers can improve feed intake, production performance, egg mass, and egg yolk chemical composition in late-laying quails

Searches for heavy long-lived charged particles with the ATLAS detector in proton-proton collisions at √s = 8 TeV

Searches for heavy long-lived charged particles are performed using a data sample of 19.1 fb−1 from proton-proton collisions at a centre-of-mass energy of s√ = 8 TeV collected by the ATLAS detector at the Large Hadron Collider. No excess is observed above the estimated background and limits are placed on the mass of long-lived particles in various supersymmetric models. Long-lived tau sleptons in models with gauge-mediated symmetry breaking are excluded up to masses between 440 and 385 GeV for tan β between 10 and 50, with a 290 GeV limit in the case where only direct tau slepton production is considered. In the context of simplified LeptoSUSY models, where sleptons are stable and have a mass of 300 GeV, squark and gluino masses are excluded up to a mass of 1500 and 1360 GeV, respectively. Directly produced charginos, in simplified models where they are nearly degenerate to the lightest neutralino, are excluded up to a mass of 620 GeV. R-hadrons, composites containing a gluino, bottom squark or top squark, are excluded up to a mass of 1270, 845 and 900 GeV, respectively, using the full detector; and up to a mass of 1260, 835 and 870 GeV using an approach disregarding information from the muon spectrometer

Design and implementation of Wireless Packet Level Authentication (WPLA)

Secure user authentication, authorization and access control have become the major challenges in any wireless security system, often due to certain wireless network characteristics such as lack of infrastructure, low power availability and mobility. Taking advantage of such network characteristies, an attacker can launch several security attacks like Denial of Service (DoS) attacks, packet spoofing and session hijacking attacks. Packet Level Authentication (PLA) provides an elegant network level solution to the aforementioned attacks by allowing every node in the network to validate the authenticity and integrity of a packet without any prior contact with the originator of the packet. The cornerstone of PLA is public key cryptography based digital signature which is added to every outgoing packet by the packet originator. Therefore, signature generation and verification schemes of PLA become infeasible in resource-constrained devices if dedicated hardware accelerator is not used. In this thesis, we present Wireless Packet Level Authentication (WPLA) that extends PLA to offer an adaptive hop-by-hop signature verification scheme. WPLA includes a lightweight signature verification approach for resource-constrained devices while retaining the pubic key cryptography based signature verification scheme for strong authentication. Furthermore, to ensure end-to-end data confidentiality over the unsecured channels, we integrate a symmetric encryption scheme along with secret key generation and distribution process. Finally, we implement the proposed solution and evaluate the performance of our implementation

Energy Efficient Computing on Multi-core Processors: Vectorization and Compression Techniques

Over the past few years, energy consumption has become the main limiting factor for computing in general. This has led CPU vendors to aggressively promote parallel computing using multiple cores without significantly increasing the thermal design power of the processor. However, achieving maximum performance and energy efficiency from the available resources on the multi-core and many-core platforms mandates efficient exploitation of the existing and emerging architectural features at the application level. This thesis presents the study of some of the existing and emerging technologies in order to identify the potential of exploiting these technologies in achieving high performance and energy efficiency for a set of Smart Grid applications on Intel multi-core and many-core platforms. The first part of this thesis explores the energy efficiency impact of different multi-core programming techniques for a selected set of benchmarks and smart grid applications on Intel SandyBridge and Haswell multi-core processors. These techniques include different parallelism techniques such as thread-level parallelism using OpenMP, task-based parallelism using OmpSs, data parallelism using SIMD (Single Instruction Multiple Data) instruction sets, code optimizations and use of different existing optimized math libraries. In our initial case studies, SIMD vectorization is proven very effective in providing both high performance and energy efficiency. Though the SIMD vectorization is proven very effective, it can also exert pressure on the available memory bandwidth for some applications like Powel Time-Series Kernel, causing under-utilization of the computing resources and thus energy inefficient executions. In the second part of this research, we investigate the opportunities of improving the performance of SIMD vectorization for memory-bound applications using SIMD data compression, SIMD software prefetching, SIMD shuffling, code-blocking and other code transformation techniques. The key idea is to reduce the data movement across memory hierarchy by using the idle CPU time. We show that integration of data compression is feasible on the Intel multicore platforms, as long as we can do it in a reasonable time. We present a comprehensive discussion on the SIMD compression techniques and the code transformations required for achieving efficient SIMD computations for memory/cache bound applications using Powel time series kernel as a demonstrator application. Finally, we perform feasibility study of SIMD optimization and compression techniques across other application domains using k-means clustering algorithm and full-search motion estimation algorithm. We also extended our experiments on Intel many-core architecture using Intel Xeon Phi coprocessor

Energy Efficiency Effects of Vectorization in Data Reuse Transformations for Many-Core Processors—A Case Study †

Thread-level and data-level parallel architectures have become the design of choice in many of today’s energy-efficient computing systems. However, these architectures put substantially higher requirements on the memory subsystem than scalar architectures, making memory latency and bandwidth critical in their overall efficiency. Data reuse exploration aims at reducing the pressure on the memory subsystem by exploiting the temporal locality in data accesses. In this paper, we investigate the effects on performance and energy from a data reuse methodology combined with parallelization and vectorization in multi- and many-core processors. As a test case, a full-search motion estimation kernel is evaluated on Intel® CoreTM i7-4700K (Haswell) and i7-2600K (Sandy Bridge) multi-core processors, as well as on an Intel® Xeon PhiTM many-core processor (Knights Landing) with Streaming Single Instruction Multiple Data (SIMD) Extensions (SSE) and Advanced Vector Extensions (AVX) instruction sets. Results using a single-threaded execution on the Haswell and Sandy Bridge systems show that performance and EDP (Energy Delay Product) can be improved through data reuse transformations on the scalar code by a factor of ≈3× and ≈6×, respectively. Compared to scalar code without data reuse optimization, the SSE/AVX2 version achieves ≈10×/17× better performance and ≈92×/307× better EDP, respectively. These results can be improved by 10% to 15% using data reuse techniques. Finally, the most optimized version using data reuse and AVX512 achieves a speedup of ≈35× and an EDP improvement of ≈1192× on the Xeon Phi system. While single-threaded execution serves as a common reference point for all architectures to analyze the effects of data reuse on both scalar and vector codes, scalability with thread count is also discussed in the paper