Auto-zero stabilized CMOS amplifiers for very low voltage or current offset

In this paper, we present two amplifiers designed in CMOS technology and including an auto-zero architecture for very low offset control

A low power and low signal 5-bit 25MS/s pipelined ADC for monolithic active pixel sensors

For CMOS monolithic active pixels sensor readout, we developed a 5 bit low power analog to digital converter using a pipelined architecture. A non-resetting sample and hold stage is included to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both the amplifier offset effect and the input common mode voltage dispersion. The converter consists of three 1.5 bit sub-ADC and a 2 bit flash. We present the results of a prototype, made of eight ADC channels. The maximum sampling rate is 25MS/s. The total DC power consumption is 1.7mW/channel on a 3.3V supply voltage recommended for the process. But at a reduced 2.5V supply, it consumes only 1.3mW. The size of each ADC channel layout is only 43μm*1.43mm. This corresponds to the pitch of two pixel columns each one would be 20μm wide. The full analog part of the converter can be quickly switched to a standby idle mode in less than 1μs; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

International audienceA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

soumis à JINSTA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35µm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1µs. The size for the layout is 80µm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20µm wide

Energy Linearity and Resolution of the ATLAS Electromagnetic Barrel Calorimeter in an Electron Test-Beam

A module of the ATLAS electromagnetic barrel liquid argon calorimeter was exposed to the CERN electron test-beam at the H8 beam line upgraded for precision momentum measurement. The available energies of the electron beam ranged from 10 to 245 GeV. The electron beam impinged at one point corresponding to a pseudo-rapidity of eta=0.687 and an azimuthal angle of phi=0.28 in the ATLAS coordinate system. A detailed study of several effects biasing the electron energy measurement allowed an energy reconstruction procedure to be developed that ensures a good linearity and a good resolution. Use is made of detailed Monte Carlo simulations based on Geant which describe the longitudinal and transverse shower profiles as well as the energy distributions. For electron energies between 15 GeV and 180 GeV the deviation of the measured incident electron energy over the beam energy is within 0.1%. The systematic uncertainty of the measurement is about 0.1% at low energies and negligible at high energies. The energy resolution is found to be about 10% sqrt(E) for the sampling term and about 0.2% for the local constant term

The Time Structure of Hadronic Showers in highly granular Calorimeters with Tungsten and Steel Absorbers

The intrinsic time structure of hadronic showers influences the timing capability and the required integration time of hadronic calorimeters in particle physics experiments, and depends on the active medium and on the absorber of the calorimeter. With the CALICE T3B experiment, a setup of 15 small plastic scintillator tiles read out with Silicon Photomultipliers, the time structure of showers is measured on a statistical basis with high spatial and temporal resolution in sampling calorimeters with tungsten and steel absorbers. The results are compared to GEANT4 (version 9.4 patch 03) simulations with different hadronic physics models. These comparisons demonstrate the importance of using high precision treatment of low-energy neutrons for tungsten absorbers, while an overall good agreement between data and simulations for all considered models is observed for steel.Comment: 24 pages including author list, 9 figures, published in JINS

Measurement of the production of a W boson in association with a charm quark in pp collisions at √s = 7 TeV with the ATLAS detector

The production of a W boson in association with a single charm quark is studied using 4.6 fb−1 of pp collision data at s√ = 7 TeV collected with the ATLAS detector at the Large Hadron Collider. In events in which a W boson decays to an electron or muon, the charm quark is tagged either by its semileptonic decay to a muon or by the presence of a charmed meson. The integrated and differential cross sections as a function of the pseudorapidity of the lepton from the W-boson decay are measured. Results are compared to the predictions of next-to-leading-order QCD calculations obtained from various parton distribution function parameterisations. The ratio of the strange-to-down sea-quark distributions is determined to be 0.96+0.26−0.30 at Q 2 = 1.9 GeV2, which supports the hypothesis of an SU(3)-symmetric composition of the light-quark sea. Additionally, the cross-section ratio σ(W + +c¯¯)/σ(W − + c) is compared to the predictions obtained using parton distribution function parameterisations with different assumptions about the s−s¯¯¯ quark asymmetry

Measurement of the top quark-pair production cross section with ATLAS in pp collisions at \sqrt{s}=7\TeV

A measurement of the production cross-section for top quark pairs(\ttbar) in $pp$ collisions at \sqrt{s}=7 \TeV is presented using data recorded with the ATLAS detector at the Large Hadron Collider. Events are selected in two different topologies: single lepton (electron $e$ or muon $\mu$) with large missing transverse energy and at least four jets, and dilepton ($ee$, $\mu\mu$ or $e\mu$) with large missing transverse energy and at least two jets. In a data sample of 2.9 pb-1, 37 candidate events are observed in the single-lepton topology and 9 events in the dilepton topology. The corresponding expected backgrounds from non-\ttbar Standard Model processes are estimated using data-driven methods and determined to be $12.2 \pm 3.9$ events and $2.5 \pm 0.6$ events, respectively. The kinematic properties of the selected events are consistent with SM \ttbar production. The inclusive top quark pair production cross-section is measured to be \sigmattbar=145 \pm 31 ^{+42}_{-27} pb where the first uncertainty is statistical and the second systematic. The measurement agrees with perturbative QCD calculations.Comment: 30 pages plus author list (50 pages total), 9 figures, 11 tables, CERN-PH number and final journal adde