Characterization of optical interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.Includes bibliographical references (p. 72-75).Interconnect has become a major issue in deep sub-micron technology. Even with copper and low-k dielectrics, parasitic effects of interconnects will eventually impede advances in integrated electronics. One technique that has the potential to provide a paradigm shift is optics. This project evaluates the feasibility of optical interconnects for distributing data and clock signals. In adopting this scheme, variation is introduced by the detector, the waveguides, and the optoelectronic circuit, which includes device, power supply and temperature variations. We attempt to characterize the effects of the aforementioned sources of variation by designing a baseline optoelectronic circuitry and fabricating a test chip which consists of the circuitry and detectors. Simulations are also performed to supplement the effort. The results are compared with the performance of traditional metal interconnects. The feasibility of optical interconnects is found to be sensitive to the optoelectronic circuitry used. Variation effects from the devices and operating conditions have profound impact on the performance of optical interconnects since they introduce substantial skew and delay in the otherwise ideal system.by Shiou Lin Sam.S.M

R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging

This report reviews current trends in the R&D of semiconductor pixellated sensors for vertex tracking and radiation imaging. It identifies requirements of future HEP experiments at colliders, needed technological breakthroughs and highlights the relation to radiation detection and imaging applications in other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory Grou

Modeling and assessment of complex interconnect features with focus on PAM-4 signal integrity

As Internet demand continues to grow, the underlying technology struggles to keep up with the ever-increasing data rates. Existing 100G Ethernet is reaching its physical limits and superior solutions need to take over. PAM-4 will be a key enabler capable of doubling the speeds of current NRZ solutions. However, it comes with its own implementation challenges, mainly from the signal integrity (SI) perspective. This thesis will evaluate the impact of complex channel characteristics on a 56 Gbps PAM-4 transmission link using SI methods. The study will be structured in three stages. First, a test board will be designed with multiple layout challenges (e.g., stackup, crosstalk, vias). Next, the effect of those designs on a PAM-4 transmission will be simulated using High-Speed Digital Design tools. Finally, results will be validated with physical measurements on a development board.Objectius de Desenvolupament Sostenible::9 - Indústria, Innovació i Infraestructura::9.b - Donar suport al desenvolupament de tecnologies, investigació i innovació nacionals als països en desenvolu­pament, garantint també un entorn normatiu propici a la diversificació industrial i l’addició de valor als productes bàsics, entre d’altre

Technology stragegy and business development at a semiconductor equipment company : a process definition and case study of a new technology

Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; in conjunction with the Leaders for Manufacturing Program at MIT, 2002.Includes bibliographical references (p. 96-100).by Christopher Lance Durham.S.M.M.B.A

Next Generation Silicon Photonic Transceiver: From Device Innovation to System Analysis

Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface

NASA SBIR abstracts of 1990 phase 1 projects

The research objectives of the 280 projects placed under contract in the National Aeronautics and Space Administration (NASA) 1990 Small Business Innovation Research (SBIR) Phase 1 program are described. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses in response to NASA's 1990 SBIR Phase 1 Program Solicitation. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 280, in order of its appearance in the body of the report. The document also includes Appendixes to provide additional information about the SBIR program and permit cross-reference in the 1990 Phase 1 projects by company name, location by state, principal investigator, NASA field center responsible for management of each project, and NASA contract number

A scalable packetised radio astronomy imager

Includes bibliographical referencesModern radio astronomy telescopes the world over require digital back-ends. The complexity of these systems depends on many site-specific factors, including the number of antennas, beams and frequency channels and the bandwidth to be processed. With the increasing popularity for ever larger interferometric arrays, the processing requirements for these back-ends have increased significantly. While the techniques for building these back-ends are well understood, every installation typically still takes many years to develop as the instruments use highly specialised, custom hardware in order to cope with the demanding engineering requirements. Modern technology has enabled reprogrammable FPGA-based processing boards, together with packet-based switching techniques, to perform all the digital signal processing requirements of a modern radio telescope array. The various instruments used by radio telescopes are functionally very different, but the component operations remain remarkably similar and many share core functionalities. Generic processing platforms are thus able to share signal processing libraries and can acquire different personalities to perform different functions simply by reprogramming them and rerouting the data appropriately. Furthermore, Ethernet-based packet-switched networks are highly flexible and scalable, enabling the same instrument design to be scaled to larger installations simply by adding additional processing nodes and larger network switches. The ability of a packetised network to transfer data to arbitrary processing nodes, along with these nodes' reconfigurability, allows for unrestrained partitioning of designs and resource allocation. This thesis describes the design and construction of the first working radio astronomy imaging instrument hosted on Ethernet-interconnected re- programmable FPGA hardware. I attempt to establish an optimal packetised architecture for the most popular instruments with particular attention to the core array functions of correlation and beamforming. Emphasis is placed on requirements for South Africa's MeerKAT array. A demonstration system is constructed and deployed on the KAT-7 array, MeerKAT's prototype. This research promises reduced instrument development time, lower costs, improved reliability and closer collaboration between telescope design teams

The impact of printed electronics on product design

Printed electronics (PE) is a disruptive but growing technology that is beginning to integrate its way into viable applications for product design. However, the potential for future impact of the technology on product design and the designer s role and contribution to this has yet to be established. Interest is increasing in the potential for product designers to explore and exploit this technology. Technologies can be seen as being disruptive from both a business, and an adoption point of view. For a business, changing from one technology to another or incorporating a new technology and its production processes can be difficult if they already have their suppliers established and existing relationships in place. Understanding and adopting a new technology can be challenging for a business and individuals working within an established industry as it can cause many questions to be raised around its performance, and direct comparison with the technology they already have in place. However, there have been many technologies that could be seen as disruptive in the past, as they offered an alternative way of working or method of manufacture, such as Bluetooth, 3D printing, and automation (manufacturing/assembly/finishing), etc., and their success has been dictated by individual s perception and adoption of the technology, with their ability to see the worth and potential in the technology. Cost comparison is also an important aspect for a business to consider when choosing whether to change to a new technology or to remain with their existing technology, as changing can disrupt the manufacturing line assembly of a product, and direct cost comparisons of components themselves, such as the cost of buying silicon components in bulk verses printing the components. The new technology needs to offer something different to a product to be worth implementing it in a product, such as its flexible form or lightweight properties of printed electronics being of benefit to the product over what a silicon electronic component/circuit could offer (restricted to rigid circuit boards), the functionality/performance of the components themselves also need to be considered. Performance, availability and maturity of the technology are some of the essential aspects to consider when incorporating a new technology into a product and these can be evaluated using a Technology Readiness Level (TRL) scale. Interest in the stage of development for a technology lies not only with designers; industry and academia also contribute to knowledge by playing a central role in the process of determining a TRL scale that is universally recognised. However, a TRL separation issue occurs between academia (often the technology only reaching an experimental proof of concept stage, a lower number on the TRL scale indicating that the technology is at an early stage of development) and industry (not considering technology for commercialisation until it reaches a stage where there is a demonstration of pre-production capability validated on economic runs, a much higher number on the TRL scale - indicating that the technology is at a much more advanced stage of development). The aim of this doctoral research was to explore the contribution of PE to product design. The researcher experienced the scientific development of the technology first-hand, and undertook a literature review that covered three main topics: 1) printed electronics (the technology itself), 2) impact (approaches to assessing impact and methods of judging new technology) because together they will identify the state of the art of printed electronics technology, and 3) education - educational theories/methods for designers - studying how designers learn, explore different methods in educating them about new technologies, and start to find appropriate methods for educating them about printed electronics technology. A knowledge framework for PE technology was generated and utilised to produce a taxonomy and TRL scale for PE and confirmed by PE expert interview. Existing case studies in which PE technology had been presented to student designers were investigated through interviews with participants from academia and industry to solicit perception and opinions on approaches for the effective communication of PE knowledge to student designers within an educational environment. The findings were interpreted using thematic analysis and, after comparing the data, three main themes identified: technical constraints, designer s perspective, and what a designer is required to do. The findings from the research were combined to create an educational approach for knowledge transfer aimed specifically at meeting the needs of product designers. This resulted in the need for PE technology to be translated into both a visual and written format to create structure and direct links between the technological elements and their form and function in order to facilitate understanding by designers. Conclusions from the research indicate that the translation of this technology into an appropriate design language will equip designers with accessible fundamental knowledge on PE technology (i.e. electrical components: form, function, and area of the technology), which will allow informed decisions to be made about how PE can be used and to utilise its benefits in the design of products. The capabilities and properties of this technology, when paired with product design practice, has the capacity to transform the designs of future products in terms of form/functionality and prevailing/views towards design approaches with electronics. If exposed to a variety of PE elements ranging across different TRLs, designers have the capacity to bridge the TRL separation issue (the gap between academia and industry) through their ability to create design solutions for an end user and provide a commercial application for the technology

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Analysis and mitigation of parallel-plate noise for high-isolation applications

Achieving highs levels of isolation between different functionalities in a PCB can be challenging. One of the major issues is that vertically adjacent planes or area fills in a PCB can form a parallel-plate waveguide with no cutoff frequency and serve as an efficient coupling mechanism between interconnects. Due to the finite size of the conductors, reflections off the edges of these parallel-plate cavities can result in the formation of standing-wave patterns with very high field strengths, resulting in high coupling at certain frequencies. This noise coupling mechanism can be suppressed by connecting the parallel plates together with an adequate amount of vias. However, adjacent power and ground conductors can not be conductively connected together because they are at different DC potentials. As a result, there is no way to eliminate the existence of parallel-plate noise in a power/ground cavity. A fundamental understanding of this problem is needed to determine how it can be mitigated. The first part of the thesis develops a qualitative understanding of the underlying physics of how noise is coupled to the parallel plates from a variety of interconnects and how the noise can spread throughout the design. This discussion is then expanded to more complex geometries that are representative of what could occur in actual designs. Test vehicles are created to study the noise coupling to various interconnects from noise injected into the power distribution network by an amplifier. Parameters affecting the transfer of noise from an amplifier to the power distribution network, such as the addition of capacitors, are then explored. An expression to predict the noise coupling using S-parameter measurements of the PCB and the amplifier is developed. It is demonstrated that results from full-wave electromagnetic simulation can be used to predict the amount of noise coupling before PCB fabrication. General design recommendations are then presented to improve design robustness to the parallel-plate noise --Abstract, page iii