4,623 research outputs found
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging
This report reviews current trends in the R&D of semiconductor pixellated
sensors for vertex tracking and radiation imaging. It identifies requirements
of future HEP experiments at colliders, needed technological breakthroughs and
highlights the relation to radiation detection and imaging applications in
other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory
Grou
Solid state television camera system Patent
Solid state television camera system consisting of monolithic semiconductor mosaic sensor and molecular digital readout system
A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner
Time-of-flight measurement is an important advancement in PET scanners to
improve image reconstruction with a lower delivered radiation dose. This
article describes the monolithic ASIC for the TT-PET project, a novel idea for
a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS
process for timing measurements, integrating a fully-depleted pixel matrix with
a low-power BJT-based front-end per channel, integrated on the same 100 thick die. The target timing resolution is 30 ps RMS for electrons from the
conversion of 511 keV photons. A novel synchronization scheme using a
patent-pending TDC is used to allow the synchronization of 1.6 million channels
across almost 2000 different chips at picosecond-level. A full-featured
demonstrator chip with a 3x10 matrix of 500x500 pixels was
produced to validate each block. Its design and experimental results are
presented here
Development of an image converter of radical design
A long term investigation of thin film sensors, monolithic photo-field effect transistors, and epitaxially diffused phototransistors and photodiodes to meet requirements to produce acceptable all solid state, electronically scanned imaging system, led to the production of an advanced engineering model camera which employs a 200,000 element phototransistor array (organized in a matrix of 400 rows by 500 columns) to secure resolution comparable to commercial television. The full investigation is described for the period July 1962 through July 1972, and covers the following broad topics in detail: (1) sensor monoliths; (2) fabrication technology; (3) functional theory; (4) system methodology; and (5) deployment profile. A summary of the work and conclusions are given, along with extensive schematic diagrams of the final solid state imaging system product
Seamless monolithic three-dimensional integration of single-crystalline films by growth
The demand for the three-dimensional (3D) integration of electronic
components is on a steady rise. The through-silicon-via (TSV) technique emerges
as the only viable method for integrating single-crystalline device components
in a 3D format, despite encountering significant processing challenges. While
monolithic 3D (M3D) integration schemes show promise, the seamless connection
of single-crystalline semiconductors without intervening wafers has yet to be
demonstrated. This challenge arises from the inherent difficulty of growing
single crystals on amorphous or polycrystalline surfaces post the
back-end-of-the-line process at low temperatures to preserve the underlying
circuitry. Consequently, a practical growth-based solution for M3D of single
crystals remains elusive. Here, we present a method for growing
single-crystalline channel materials, specifically composed of transition metal
dichalcogenides, on amorphous and polycrystalline surfaces at temperatures
lower than 400 {\deg}C. Building on this developed technique, we demonstrate
the seamless monolithic integration of vertical single-crystalline logic
transistor arrays. This accomplishment leads to the development of
unprecedented vertical CMOS arrays, thereby constructing vertical inverters.
Ultimately, this achievement sets the stage to pave the way for M3D integration
of various electronic and optoelectronic hardware in the form of single
crystals
A survey of carbon nanotube interconnects for energy efficient integrated circuits
This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design
- …