Threshold Voltage and Leakage Current Variability on Process Parameter in a 22 nm PMOS device

This article explains the effect of variation on the process parameters while designing a Nano-scaled planar PMOS device in complementary metal-oxide-semiconductor (CMOS) technology for 22 nm gate length. This procedure aims to meet the best combination of fabrication process parameter on the threshold voltage (VTH) and leakage current (IOFF) which was predicted by the International Technology Roadmap for Semiconductors (ITRS). The gate structure of the PMOS device consists of Titanium Dioxide (TiO2) as the high permittivity material (high-k) dielectric and Tungsten Silicide (WSix) metal gate where it is deposited on top of the TiO2 high-k layer. The simulation process was designed using an industrial-based numerical simulator. This simulator was then aided in design with the L9 Taguchi’s orthogonal array method to optimise the best combination of process parameters in order to achieve the optimum VTH value with the lowest IOFF. The analysis results of the factor effect on the SNR in ANOVA analysis clearly show that the Halo implantation tilting angle has the greatest influence with 52.47% in optimising the process parameter where the implantation tilting angle is at 35°. The final results in characterizing and modelling the process parameters of the 22 nm PMOS device with reference to the prediction ITRS succeeded where the result of the VTH is 4.25% closest to the prediction value of -0.289 V ± 12.7% and minimum IOFF value which is 92% away from the predicted value which is 100 nA/µm

Control Factors Optimization on Threshold Voltage and Leakage Current in 22 nm NMOS Transistor Using Taguchi Method

In this article, Taguchi method was used to optimize the control factor in obtaining the optimal value which is also known as response characteristics, where the threshold voltage (Vth) and leakage current (Ileak) for NMOS transistor with a gate length of 22 nm is taken into account. The NMOS transistor design includes a high permittivity material (high-k) as a dielectric layer and a metal gate which is Titanium Dioxide (TiO2) and Tungsten Silicide (WSiX) respectively. The control factor was optimized in designing the NMOS device using the Taguchi Orthogonal Array Method where the Signal-to-Noise Ratio (SNR) analysis uses the Nominal-the-Best (NTB) SNR for Vth, while for Ileak analysis, a Smaller-the-Better (STB) SNR was used. Four manufacturing control factors and two noise factor are used to optimize the response characteristics and find the best combination of design parameters. The results show that the Halo implantation tilting angle is the dominant factor where it has the greatest factor effect on the SNR of the Ileak with 55.52%. It is also shown that the values of Vth have the least variance and the mean value can be set to 0.289 V ± 12.7% and Ileak is less than 100 nA/µm which is in line with the projections made by the International Technology Roadmap for Semiconductors (ITRS)

EuFe2_2As2_2 under high pressure: an antiferromagnetic bulk superconductor

We report the ac magnetic susceptibility $\chi_{ac}$ and resistivity $\rho$ measurements of EuFe$_2$As$_2$ under high pressure $P$. By observing nearly 100% superconducting shielding and zero resistivity at $P$ = 28 kbar, we establish that $P$-induced superconductivity occurs at $T_c \sim$~30 K in EuFe$_2$As$_2$. $\rho$ shows an anomalous nearly linear temperature dependence from room temperature down to $T_c$ at the same $P$. $\chi_{ac}$ indicates that an antiferromagnetic order of Eu$^{2+}$ moments with $T_N \sim$~20 K persists in the superconducting phase. The temperature dependence of the upper critical field is also determined.Comment: To appear in J. Phys. Soc. Jpn., Vol. 78 No.

The BaBar detector: Upgrades, operation and performance

Contains fulltext : 121729.pdf (preprint version ) (Open Access