Minimizing and exploiting leakage in VLSI

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally dynamic (switching) power has dominated the total power consumption of VLSI circuits. However, due to process scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. This dissertation explores techniques to reduce leakage, as well as techniques to exploit leakage currents through the use of sub-threshold circuits. This dissertation consists of two studies. In the first study, techniques to reduce leakage are presented. These include a low leakage ASIC design methodology that uses high VT sleep transistors selectively, a methodology that combines input vector control and circuit modification, and a scheme to find the optimum reverse body bias voltage to minimize leakage. As the minimum feature size of VLSI fabrication processes continues to shrink with each successive process generation (along with the value of supply voltage and therefore the threshold voltage of the devices), leakage currents increase exponentially. Leakage currents are hence seen as a necessary evil in traditional VLSI design methodologies. We present an approach to turn this problem into an opportunity. In the second study in this dissertation, we attempt to exploit leakage currents to perform computation. We use sub-threshold digital circuits and come up with ways to get around some of the pitfalls associated with sub-threshold circuit design. These include a technique that uses body biasing adaptively to compensate for Process, Voltage and Temperature (PVT) variations, a design approach that uses asynchronous micro-pipelined Network of Programmable Logic Arrays (NPLAs) to help improve the throughput of sub-threshold designs, and a method to find the optimum supply voltage that minimizes energy consumption in a circuit

The Automatic Synthesis of Fault Tolerant and Fault Secure VLSI Systems

This thesis investigates the design of fault tolerant and fault secure (FTFS) systems within the framework of silicon compilation. Automatic design modification is used to introduce FTFS characteristics into a design. A taxonomy of FTFS techniques is introduced and is used to identify a number of features which an "automatic design for FTFS" system should exhibit. A silicon compilation system, Chip Churn 2 (CC2), has been implemented and has been used to demonstrate the feasibility of automatic design of FTFS systems. The CC2 system provides a design language, simulation facilities and a back-end able to produce CMOS VLSI designs. A number of FTFS design methods have been implemented within the CC2 environment; these methods range from triple modular redundancy to concurrent parity code checking. The FTFS design methods can be applied automatically to general designs in order to realise them as FTFS systems. A number of example designs are presented; these are used to illustrate the FTFS modification techniques which have been implemented. Area results for CMOS devices are presented; this allows the modification methods to be compared. A number of problems arising from the methods are highlighted and some solutions suggested

Digital Circuit Design Using Floating Gate Transistors

Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the design’s delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using don’t cares. Our optimization approach distinguishes itself from other optimization techniques that use don’t cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs

Digital Circuit Design Using Floating Gate Transistors

Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the design’s delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using don’t cares. Our optimization approach distinguishes itself from other optimization techniques that use don’t cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

Cholinergic mechanisms in depression

Evidence supporting a cholinergic hypothesis of depression is presented. First, cholinergic overdrive produces behavioral, neuroendocrine, and polysomnographic features of melancholia, and melancholics exhibit state-independent supersensitivity to cholinergic overdrive. Drugs inducing up-regulation and supersensitivity of cholinergic systems produce behavioral, polysomnographic, and neuroendocrine effects of melancholia when withdrawn. These observations also implicate cholinergic system supersensitivity as a factor in the pathophysiology of certain affective disorders. Cholinergic and monoaminergic mechanisms reciprocally regulate drive-reduction, and substances of abuse either activate monoaminergic networks or antagonize cholinergic systems. These points are consistent with the hypothesis that dynamic interaction between cholinergic and monoaminergic systems is involved in the regulation of mood and affect. Finally, antimuscarinic agents have antidepressant effects. Thus, the hypothesis that supersensitivity of cholinergic systems is involved in the pathophysiology of affective disorders is supported by several lines of evidence. This evidence is reviewed; directions for future research and promising methods of investigation are discussed.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/26059/1/0000133.pd

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Learning in clustered spiking networks

Neurons spike on a millisecond time scale while behaviour typically spans hundreds of milliseconds to seconds and longer. Neurons have to bridge this time gap when computing and learning behaviours of interest. Recent computational work has shown that neural circuits can bridge this time gap when connected in specific ways. Moreover, the connectivity patterns can develop using plasticity rules typically considered to be biologically plausible. In this thesis, we focus on one type of connectivity where excitatory neurons are grouped in clusters. Strong recurrent connectivity within the clusters reverberates the activity and prolongs the time scales in the network. This way, the clusters of neurons become the basic functional units of the circuit, in line with an increasing number of experimental studies. We study a general architecture where plastic synapses connect the clustered network to a read-out network. We demonstrate the usefulness of this architecture for two different problems: 1) learning and replaying sequences; 2) learning statistical structure. The time scales in both problems range from hundreds of milliseconds to seconds and we address the problems through simulation and analysis of spiking networks. We show that the clustered organization circumvents the need for non-bio-plausible mathematical optimizations and instead allows the use of unsupervised spike-timing-dependent plasticity rules. Additionally, we make qualitative links to experimental findings and predictions for both problems studied. Finally, we speculate about future directions that could extend upon our findings.Open Acces

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Chinesische und indische Direktinvestitionen in Deutschland - Muster, Auswirkungen und Reaktionen in globalen Produktionsnetzwerken

Seit den 1970er Jahren liegt das Wirtschaftswachstum in einigen Ländern mit geringem Pro-Kopf-Einkommen deutlich über dem Wachstum in Industriestaaten. Aus diesen als Emerging Markets benannten Ländern investieren Unternehmen (Emerging Market Firms / EMFs) zunehmend im Ausland. EMFs werden zwar als neue Determinante der Globalisierung der Wirtschaft anerkannt, es gibt aber bislang nur wenige Untersuchungen dieses Phänomens. Zudem stehen sich Akteure mit befürwortenden und ablehnenden Haltungen gegenüber. Diesen Akteuren fehlt eine empirische Grundlage, um faktenbasiert über die Folgen der Investitionen von EMFs zu diskutieren. Chinesische und indische Unternehmen sind wesentliche Vertreter der EMFs und investieren in zunehmendem Maße auch in Deutschland. Innerhalb dieser Arbeit werden Investitionen aus diesen Herkunftsländern in dieses Zielland analysiert, um EMFs exemplarisch zu untersuchen und die Eigenschaften der Unternehmen sowie die Folgen der Investitionen konzeptionell einzuordnen. Dafür wird der Ansatz der Globalen Produktionsnetzwerke (GPN) als Rahmen genutzt und die Kategorien Wert, Macht und Einbettung des Ansatzes um Theorien aus Nachbardisziplinen erweitert. EMFs werden innerhalb der Arbeit als die agierenden Organisationen angesehen, deren Handlungen Einfluss auf im Zielland vorhandene Stakeholder haben. Im Fokus stehen übernommene Unternehmen sowie deren Kunden, Zulieferer und Konkurrenten sowie Arbeitnehmer. Die in der Empirie untersuchten ökonomischen Entwicklungen werden aus einer relationalen Perspektive betrachtet. Die empirischen Instrumente sind daher darauf ausgelegt, Pfadabhängigkeiten ebenso wie nicht-rationale Einflussfaktoren zu berücksichtigen. Die vorliegende Arbeit baut auf bestehenden Veröffentlichungen auf, in denen die Gründe von EMFs für ausländische Direktinvestitionen (ADI) verallgemeinert dargestellt werden oder Ergebnisse zu den Auswirkungen nach einem Zusammenschluss oder einer Akquisition (Merger & Acquisition / M&A) auf geringen Fallzahlen basieren und nicht konzeptionell eingeordnet werden. In bestehenden Veröffentlichungen werden überwiegend negative Folgen der Investitionen herausgestellt. In den für diese Arbeit durchgeführten empirischen Erhebungen werden die bestehenden Ergebnisse geprüft und innerhalb des erweiterten GPN-Ansatzes konzeptionalisiert. Die deskriptiv-statistische Analyse chinesischer und indischer Unternehmen mit Beteiligungen in Deutschland ergibt, dass sie als heterogene Akteure gesehen werden müssen. Die Unternehmen verteilen sich unterschiedlich auf Wirtschaftszweige und wählen je nach Ziel und Größe der Unternehmen entweder eine Greenfield- oder Brownfield-Investition. Bestehende, zusammenfassende Bezeichnungen werden der identifizierten Heterogenität nicht gerecht. Solche Fälle, in denen ein bestehendes deutsches Unternehmen übernommen wurde, werden durch qualitative Interviews detailliert untersucht und die Auswirkungen und Reaktionen exemplarisch vorgestellt. Es wird aufgezeigt, dass ein erweiterter GPN-Ansatz genutzt werden kann, um die Gründe für eine Internationalisierung über Akquisen ebenso zu entwickeln, wie die zu erwartenden Auswirkungen. Es wird erarbeitet, dass gegensätzliche Ausprägungen in den Kategorien Wert und Macht auf Seiten des kaufenden und akquirierten Unternehmens keine direkten negativen Auswirkungen für die übernommenen Unternehmen bedeuten. Unterstützt wird dieses auf harten Faktoren basierende Ergebnis – wie geringe Qualität auf Seiten des kaufenden Unternehmens – durch die Bedeutung der Einbettung. Eine fehlende räumliche Einbettung der EMFs in Europa führt ebenso wie die fehlende Einbettung in Netzwerke und ein fehlendes Verständnis für die gesellschaftliche Einbettung dazu, dass die Auswirkungen für übernommene Unternehmen nicht negativ sind. Die drei Kategorien erlauben somit die Entwicklung einer differenzierten – nicht generalisierenden – Betrachtung, in der eine kontingente Sichtweise eingenommen wird. Unter Berücksichtigung der Governance-Form der Kunden- und Zulieferbeziehungen werden in der Arbeit außerdem spezifische Auswirkungen und Reaktionen der im Produktionsprozess vor- und nachgelagerten Unternehmen der Wertkette untersucht und konzeptualisiert. Mit dem ergänzten GPN-Ansatz ist zusammenfassend ein theoretisches Instrument entwickelt worden, welches genutzt werden kann, um die Eigenschaften und die Internationalisierung von EMFs sowie die Auswirkungen dieser ADI auf die Wertketten von Unternehmen in Industriestaaten zu untersuchen