Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, highspeed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field

Ferroelectric HfO2 for Emerging Ferroelectric Semiconductor Devices

The spontaneous polarization in ferroelectrics (FE) makes them particularly attractive for non-volatile memory and logic applications. Non-volatile FRAM memories using perovskite structure materials, such as Lead Zirconate Titanate (PZT) and Strontium Bismuth Tantalate (SBT) have been studied for many years. However, because of their scaling limit and incompatibility with CMOS beyond 130 nm node, floating gate Flash memory technology has been preferred for manufacturing. The recent discovery of ferroelectricity in doped HfO2 in 2011 has opened the door for new ferroelectric based devices compatible with CMOS technology, such as Ferroelectric Field Effect Transistor (FeFET) and Ferroelectric Tunnel Junctions (FTJ). This work began with developing ferroelectric hysteresis characterization capabilities at RIT. Initially reactively sputtered aluminum doped HfO2 films were investigated. It was observed that the composition control using co-sputtering was not achievable within the existing capabilities. During the course of this study, collaboration was established with the NaMLab group in Germany to investigate Si doped HfO2 deposited by Atomic Layer Deposition (ALD). Metal Ferroelectric Metal (MFM) devices were fabricated using TiN as the top and bottom electrode with Si:HfO2 thickness ranging from 6.4 nm to 22.9 nm. The devices were electrically tested for P-E, C-V and I-V characteristics. Structural characterizations included TEM, EELS, XRR, XRD and XPS/Auger spectroscopy. Higher remanant polarization (Pr) was observed for films of 9.3 nm and 13.1 nm thickness. Thicker film (22.9 nm) showed smaller Pr. Devices with 6.4 nm thick films exhibit tunneling behavior showing a memristor like I-V characteristics. The tunnel current and ferroelectricity showed decrease with cycling indicating a possible change in either the structure or the domain configurations. Theoretical simulations using the improved FE model were carried out to model the ferroelectric behavior of different stacks of films

Integration of Ferroelectric HfO2 onto a III-V Nanowire Platform

The discovery of ferroelectricity in CMOS-compatible oxides, such as doped hafnium oxide, has opened new possibilities for electronics by reviving the use of ferroelectric implementations on modern technology platforms. This thesis presents the ground-up integration of ferroelectric HfO2 on a thermally sensitive III-V nanowire platform leading to the successful implementation of ferroelectric transistors (FeFETs), tunnel junctions (FTJs), and varactors for mm-wave applications. As ferroelectric HfO2 on III-V semiconductors is a nascent technology, a special emphasis is put on the fundamental integration issues and the various engineering challenges facing the technology.The fabrication of metal-oxide-semiconductor (MOS) capacitors is treated as well as the measurement methods developed to investigate the interfacial quality to the narrow bandgap III-V materials using both electrical and operando synchrotron light source techniques. After optimizing both the films and the top electrode, the gate stack is integrated onto vertical InAs nanowires on Si in order to successfully implement FeFETs. Their performance and reliability can be explained from the deeper physical understanding obtained from the capacitor structures.By introducing an InAs/(In)GaAsSb/GaSb heterostructure in the nanowire, a ferroelectric tunnel field effect transistor (ferro-TFET) is fabricated. Based on the ultra-short effective channel created by the band-to-band tunneling process, the localized potential variations induced by single ultra-scaled ferroelectric domains and individual defects are sensed and investigated. By intentionally introducing a gate-source overlap in the ferro-TFET, a non-volatile reconfigurable single-transistor solution for modulating an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing is implemented.Finally, by fabricating scaled ferroelectric MOS capacitors in the front-end with a dedicated and adopted RF and mm-wave backend-of-line (BEOL) implementation, the ferroelectric behavior is captured at RF and mm-wave frequencies

III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors

With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2

Ferroelectric-Semiconductor Systems for New Generation of Solar Cells

This dissertation includes two parts. In the first part the study is focused on the fabrication of multifunctional thin films for photovoltaic applications. There is no doubt about the importance of transforming world reliance from traditional energy resources, mainly fossil fuel, into renewable energies. Photovoltaic section still owns very small portion of the production, despite its fast growth and vast research investments. New methods and concepts are proposed in order to improve the efficiency of traditional solar cells or introduce new platforms. Recently, ferroelectric photovoltaics have gained interest among researchers. First objective in application of ferroelectric material is to utilize its large electric field as a replacement for or improvement of built-in electric field in semiconductor p-n junctions which is responsible for the separation of generated electron-hole pairs. Increase in built in electric field will increase open-circuit voltage of the solar cell. In this regard, thin films of ferroelectric hafnium dioxide doped with silicon have been fabricated using physical vapor deposition techniques. Scanning probe microscopy techniques (PFM and KPFM) have been employed to analyze ferroelectric response and surface potential of the sample. The effects of poling direction of the ferroelectric film on the surface potential and current-voltage characteristics of the cell have been investigated. The results showed that the direction of poling affects photoresponse of the cell and based on the direction it can either improved or diminished. In the second part of this work, epitaxial thin films have been synthesized with physical vapor deposition techniques such as sputtering and electron beam evaporation for the ultimate goal of producing multifunctional three-dimensional structures. Three-dimensional structures have been used for applications such as magnetic sensors, filters, micro-robots and can be used for modification of the surface of solar cells in order to improve light absorption and efficiency. One of the important techniques for producing 3-D structures is using origami techniques. The effectiveness of this technique depends on the control of parameters which define direction of bending and rolling of the film or curvature of the structure based on the residual stress in the structure after film’s release and on the quality and uniformity of the film. In epitaxially grown films, the magnitude and direction of the stress are optimized, so the control over direction of rolling or bending of the film can be controlled more accurately. For this purpose, deposition conditions for epitaxy of Zn, Fe, Ru, Ti, NaCl and Cr on Si, Al2O3 or MgO substrates have been investigated and optimized. Crystallinity, composition and morphology of the films were characterized using reflective high energy diffraction (RHEED), Auger electron spectroscopy (AES), energy dispersive X-ray (EDX), and scanning electron microscopy (SEM)

Towards Oxide Electronics:a Roadmap

At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore's law is approaching the insurmountable barrier given by the ultimate atomic nature of matter. A major challenge for 21st century scientists is finding novel strategies, concepts and materials for replacing silicon-based CMOS semiconductor technologies and guaranteeing a continued and steady technological progress in next decades. Among the materials classes candidate to contribute to this momentous challenge, oxide films and heterostructures are a particularly appealing hunting ground. The vastity, intended in pure chemical terms, of this class of compounds, the complexity of their correlated behaviour, and the wealth of functional properties they display, has already made these systems the subject of choice, worldwide, of a strongly networked, dynamic and interdisciplinary research community. Oxide science and technology has been the target of a wide four-year project, named Towards Oxide-Based Electronics (TO-BE), that has been recently running in Europe and has involved as participants several hundred scientists from 29 EU countries. In this review and perspective paper, published as a final deliverable of the TO-BE Action, the opportunities of oxides as future electronic materials for Information and Communication Technologies ICT and Energy are discussed. The paper is organized as a set of contributions, all selected and ordered as individual building blocks of a wider general scheme. After a brief preface by the editors and an introductory contribution, two sections follow. The first is mainly devoted to providing a perspective on the latest theoretical and experimental methods that are employed to investigate oxides and to produce oxide-based films, heterostructures and devices. In the second, all contributions are dedicated to different specific fields of applications of oxide thin films and heterostructures, in sectors as data storage and computing, optics and plasmonics, magnonics, energy conversion and harvesting, and power electronics

HfO₂-based ferroelectrics:From enhancing performance, material design, to applications

Nonvolatile memories are in strong demand due to the desire for miniaturization, high-speed storage, and low energy consumption to fulfill the rapid developments of big data, the Internet of Things, and artificial intelligence. Hafnia (HfO2)-based materials have attracted significant interest due to the advantages of complementary-metal-oxide-semiconductor (CMOS) compatibility, large coercive voltage, and superior ferroelectricity at an ultra-thin thickness. The comparable ferroelectricity to that of traditional perovskite materials and size advantage of HfO2 result in fascinating storage performance, which can be readily applicable to the fields of integrated non-volatile memories. This Review provides a comprehensive overview of recent developments in HfO2-based ferroelectrics with attention to the origin of ferroelectricity, performance modulation, and recent achievements in the material. Moreover, potential solutions to existing challenges associated with the materials are discussed in detail, including the wake-up effect, long-term fatigue behavior, and imprint challenges, which pave the way for obtaining HfO2-based ferroelectric materials and devices with long service life and high stability. Finally, the range of potential applications for these fascinating new materials is presented and summarized, which include non-volatile memories and neuromorphic systems. This Review intends to present the state-of-the-art HfO2-based ferroelectrics and to highlight the current challenges, possible applications, and future opportunities and can act as an update for recent developments in these intriguing materials and provide guidance for future researchers in the design and optimization of HfO2-based ferroelectric materials and devices. </p

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications