Digital ADCs and ultra-wideband RF circuits for energy constrained wireless applications by Denis Clarke Daly.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 173-183).Ongoing advances in semiconductor technology have enabled a multitude of portable, low power devices like cellular phones and wireless sensors. Most recently, as transistor device geometries reach the nanometer scale, transistor characteristics have changed so dramatically that many traditional circuits and architectures are no longer optimal and/or feasible. As a solution, much research has focused on developing 'highly digital' circuits and architectures that are tolerant of the increased leakage, variation and degraded voltage headrooms associated with advanced CMOS processes. This thesis presents several highly digital, mixed-signal circuits and architectures designed for energy constrained wireless applications. First, as a case study, a highly digital, voltage scalable flash ADC is presented. The flash ADC, implemented in 0.18 [mu]m CMOS, leverages redundancy and calibration to achieve robust operation at supply voltages from 0.2 V to 0.9 V. Next, the thesis expands in scope to describe a pulsed, noncoherent ultra-wideband transceiver chipset, implemented in 90 nm CMOS and operating in the 3-to-5 GHz band. The all-digital transmitter employs capacitive combining and pulse shaping in the power amplifier to meet the FCC spectral mask without any off-chip filters. The noncoherent receiver system-on-chip achieves both energy efficiency and high performance by employing simple amplifier and ADC structures combined with extensive digital calibration. Finally, the transceiver chipset is integrated in a complete system for wireless insect flight control.(cont.) Through the use of a flexible PCB and 3D die stacking, the total weight of the electronics is kept to 1 g, within the carrying capacity of an adult Manduca sexta moth. Preliminary wireless flight control of a moth in a wind tunnel is demonstrated.Ph.D

Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems

With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device uncertainties, such as process, voltage, and temperature variations. To ensure system reliability, worst-case corner assumptions are usually made in each design level. However, the over-pessimistic worst-case margin leads to unnecessary power waste and performance loss as high as 2.2x. Since optimizations are traditionally confined to each specific level, those safe margins can hardly be properly exploited. To tackle the challenge, it is therefore advised in this Ph.D. thesis to perform a cross-layer optimization for digital signal processing circuits and systems, to achieve a global balance of power consumption and output quality. To conclude, the traditional over-pessimistic worst-case approach leads to huge power waste. In contrast, the adaptive voltage scaling approach saves power (25% for the CORDIC application) by providing a just-needed supply voltage. The power saving is maximized (46% for CORDIC) when a more aggressive voltage over-scaling scheme is applied. These sparsely occurred circuit errors produced by aggressive voltage over-scaling are mitigated by higher level error resilient designs. For functions like FFT and CORDIC, smart error mitigation schemes were proposed to enhance reliability (soft-errors and timing-errors, respectively). Applications like Massive MIMO systems are robust against lower level errors, thanks to the intrinsically redundant antennas. This property makes it applicable to embrace digital hardware that trades quality for power savings.Comment: 190 page

Digital-based analog processing in nanoscale CMOS ICs for IoT applications

The Internet-of-Things (IoT) concept has been opening up a variety of applications, such as urban and environmental monitoring, smart health, surveillance, and home automation. Most of these IoT applications require more and more power/area efficient Complemen tary Metal–Oxide–Semiconductor (CMOS) systems and faster prototypes (lower time-to market), demanding special modifications in the current IoT design system bottleneck: the analog/RF interfaces. Specially after the 2000s, it is evident that there have been significant improvements in CMOS digital circuits when compared to analog building blocks. Digital circuits have been taking advantage of CMOS technology scaling in terms of speed, power consump tion, and cost, while the techniques running behind the analog signal processing are still lagging. To decrease this historical gap, there has been an increasing trend in finding alternative IC design strategies to implement typical analog functions exploiting Digital in-Concept Design Methodologies (DCDM). This idea of re-thinking analog functions in digital terms has shown that Analog ICs blocks can also avail of the feature-size shrinking and energy efficiency of new technologies. This thesis deals with the development of DCDM, demonstrating its compatibility for Ultra-Low-Voltage (ULV) and Power (ULP) IoT applications. This work proves this state ment through the proposing of new digital-based analog blocks, such as an Operational Transconductance Amplifiers (OTAs) and an ac-coupled Bio-signal Amplifier (BioAmp). As an initial contribution, for the first time, a silicon demonstration of an embryonic Digital-Based OTA (DB-OTA) published in 2013 is exhibited. The fabricated DB-OTA test chip occupies a compact area of 1,426 µm2 , operating at supply voltages (VDD) down to 300 mV, consuming only 590 pW while driving a capacitive load of 80pF. With a Total Harmonic Distortion (THD) lower than 5% for a 100mV input signal swing, its measured small-signal figure of merit (FOMS) and large-signal figure of merit (FOML) are 2,101 V −1 and 1,070, respectively. To the best of this thesis author’s knowledge, this measured power is the lowest reported to date in OTA literature, and its figures of merit are the best in sub-500mV OTAs reported to date. As the second step, mainly due to the robustness limitation of previous DB-OTA, a novel calibration-free digital-based topology is proposed, named here as Digital OTA (DIG OTA). A 180-nm DIGOTA test chip is also developed exhibiting an area below the 1000 µm2 wall, 2.4nW power under 150pF load, and a minimum VDD of 0.25 V. The proposed DIGOTA is more digital-like compared with DB-OTA since no pseudo-resistor is needed. As the last contribution, the previously proposed DIGOTA is then used as a building block to demonstrate the operation principle of power-efficient ULV and ultra-low area (ULA) fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA) such as extreme low area Body Dust. Measured results in 180nm CMOS confirm that the proposed BioDIGOTA can work with a supply voltage down to 400 mV, consuming only 95 nW. The BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22X times compared to the current state of the art while keeping reasonable system performance, such as 7.6 Noise Efficiency Factor (NEF) with 1.25 µVRMS input-referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of the common-mode rejection ratio (CMRR) and 55 dB of power supply rejection ratio (PSRR). After reviewing the current DCDM trend and all proposed silicon demonstrations, the thesis concludes that, despite the current analog design strategies involved during the analog block development

Digital-Based Analog Processing in Nanoscale CMOS ICs for IoT Applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Silicon Photonic Platforms and Systems for High-speed Communications

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform

Fault-tolerant design of RF front-end circuits

The continuing trends of scaling in the CMOS industry have, inevitably, been accompanied by an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Two main reasons have contributed to the fact that fault-tolerant solutions for circuits that operate in the GHz domain have not been realized so far. First, GHz signals are extremely sensitive to higher-order effects such as stray pick-ups, interference, package & on-chip parasitics, etc. Secondly, the use of passives, especially inductors, in the feedback path poses huge area overheads, in addition to a slew of instability problems due to wide variations and soft faults. Hence traditional fault-tolerance methods used in digital and low frequency analog circuits cannot be applied in the RF domain. This work presents a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique is minimally intrusive and is transparent during \u27normal\u27 use of the circuit. It is characterized by low area and power overheads, does not need any off-chip computing or DSP cores, and is characterized by self-correction times in the range of a few hundreds of microseconds. It compares very well with existing commercial RF test solutions that use DSP cores and require hundreds of milliseconds. The methodology is demonstrated on a LNA, since it is critical for the performance of the entire front-end. It is validated with simulation and fabrication results of the system designed in IBM 0.25 µm CMOS 6RF process

Development of high-performance, cost-effective quantum dot lasers for data-centre and Si photonics applications

Photonic technologies have been considered new methods to achieve high bandwidth data communication and transmission. Si-photonics was proposed to address the discrepancy between bulky photonic devices and advanced electronics and create high-density integrated photonics. One of the challenges is integrating all the components necessary for full-functionality photonic integrated circuits (PIC). Great efforts have been devoted to overcoming the inherent limitations of Group-IV materials to provide sufficient gain, efficient modulation and sensitive detections. Making Si the host material for efficient light emission poses the most stringent requirements and is the primary missing component in the Si-photonics platform. Incorporating III-V materials with the Si photonics platform and quantum dot (QD) structure is a promising solution to the problem of a fully-integrated and high-functioning PIC. High-performance QD lasers on III-V substrate or epitaxially on silicon have been developed in the last few decades with low threshold current density, low-temperature sensitivity, great reliability and large injection efficiency. Moreover, from the dynamic aspect, the intrinsic frequency of direct modulated laser and noise intensity is important for its applications in a data centre. QD is considered an alternative to quantum wells (QWs); however, the demonstrated QD laser has not fulfilled initial expectations, mainly due to its high gain compression and low differential gain. Another feature that needs to be noticed is feedback sensitivity, as the properties of semiconductor lasers are greatly degraded by reflection from external reflectors, such as the fibre connects and facets of integrated devices. QD devices are predicted to have stronger feedback resistance due to their large damping and small linewidth enhancement factor (LEF). These properties have attracted much research, and high-performance QD devices have been developed. In this thesis, we comprehensively investigated QD laser performance and applied our QD laser in the optical module instead of the commercial QW distributed feedback (DFB) laser. The background of Si photonics, the development of QD devices, and the fundamentals of QD lasers are presented in Chapter 1. The basic static and dynamic performances are demonstrated in Chapters 2 and 3. The GaAs-based QD laser provides a low threshold, high-temperature stability, and low noise operation with a limited small signal bandwidth. Chapter 4 provides a comprehensive study of the feedback resistance of the QD laser. The onset of coherence collapse is determined as -14 dB, verified by the static optical and electrical spectra and small signal response. Based on previous measurements, the QD laser is proven to be a high-performance, low-cost candidate for the Si-photonics module. In Chapter 5, the QD laser is used in practical applications, including a large signal transmission system with and without feedback and a commercial optical module. Although the intrinsic bandwidth of the QD laser is limited to around 5GHz due to the large damping and unoptimised capacitance, 30 Gbps data transmission has been demonstrated by a directly modulated QD laser. Large, high-speed signal modulation is achieved due to its high gain compression factor. Regarding the laser with intentional feedback, there is little degradation in the eye diagram under the whole feedback level up to -8dB. We also replaced the commercial QW DFB laser in 100G data-centre reach (DR)-1 optical module with our QD Fabry Perot (FP) laser without an isolator which gives a clear eye diagram under 53 Gbps 4-level pulse amplitude modulation (PAM4) with an extinction ratio (ER) of 4.7 dB. In conclusion, this thesis verifies the feasibility of adopting the QD laser as a light source for the Si-photonics module. The QD laser is selected over other lasers because of its low threshold, high-temperature stability and maximum operating temperature, and strong tolerance to unintentional feedback. This is the first project to measure critical feedback levels with different characteristics and to theoretically analyse the inconsistent value. More importantly, this thesis’ most original contribution is investigating the commercial applications of QD lasers in a Si-photonics module in an isolator-free state. In summary, the QD laser has been proven to be a feasible solution for the next-generation optical system

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields