Simulations of CMOS pixel sensors with a small collection electrode, improved for a faster charge collection and increased radiation tolerance

CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel sizes larger than approximately forty micrometers. This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations. The studied design uses a 0.18 micrometer process implemented on a high-resistivity epitaxial layer.Comment: Proceedings of the PIXEL 2018 Worksho

Front end electronics for pixel detector of the PANDA MVD

ToPix 2.0 is a prototype in a CMOS 0.13 ¹m technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 ¹W/cell). In an area of 100¹m£100¹m each cell incorporates the analog and digital electronics necessary to amplify the detector signal and to digitize the time and charge information. The ASIC includes 320 pixel readout cells organized in four columns and a simplified version of the end of column readout

Test-beam Performance Results of the FASTPIX Sub-Nanosecond CMOS Pixel Sensor Demonstrator

Within the ATTRACT FASTPIX project, a monolithic pixel sensor demonstrator chip has been developed in a modified 180 nm CMOS imaging process technology, targeting sub-nanosecond timing precision for single ionising particles. It features a small collection electrode design on a 25 micrometers-thick epitaxial layer and contains 32 mini matrices of 68 hexagonal pixels each, with pixel pitches ranging from 8.66 to 20 micrometers. Four pixels are transmitting an analog output signal and 64 are transmitting binary hit information. Various design variations are explored, aiming at accelerating the charge collection and making the timing of the charge collection more uniform over the pixel area. Signal treatment of the analog waveforms, as well as reconstruction of digital position, time and charge information, is carried out off-chip. This contribution introduces the design of the sensor and readout system and presents performance results for various pixel designs achieved in recent test beam measurements with external tracking and timing reference detectors. A time resolution below 150 ps is obtained at full efficiency for all pixel pitches.Comment: 14 pages, 15 figures, submitted to NIMA (special issue for ULITIMA 2023 conference

Comparison of small collection electrode CMOS pixel sensors with partial and full lateral depletion of the high-resistivity epitaxial layer

Large area silicon pixel trackers are currently under development for the High Luminosity upgrade of the LHC detectors. They are also foreseen for the detectors proposed for the future high energy Compact Linear Collider CLIC. For the CLIC tracker a single hit resolution of 7 μm, a timing resolution of a few nanoseconds and a material budget of 1–2 % of radiation length per detection layer are required. Integrated CMOS technologies are promising candidates to reduce the cost, facilitate the production and to achieve a low material budget. CMOS sensors with a small size of the collection electrode benefit from a small sensor capacitance, resulting in a large signal to noise ratio and a low power consumption. The Investigator is a test-chip developed for the ALICE Inner Tracking System upgrade, implemented in a 180 nm CMOS process with a small collection electrode on a high resistivity epitaxial layer. The Investigator has been produced in different process variants: the standard process and a modified process, where an additional N-layer has been inserted to obtain full lateral depletion. This paper presents a comparison of test-beam results for both process variants, focuses on spatial and timing resolution as well as efficiency measurements

High-rate, high-resolution single photon X-ray imaging: Medipix4, a large 4-side buttable pixel readout chip with high granularity and spectroscopic capabilities

The Medipix4 chip is the latest member in the Medipix/Timepix family of hybrid pixel detector chips aimed at high-rate spectroscopic X-ray imaging using high-Z materials. It can be tiled on all 4 sides making it ideal for constructing large-area detectors with minimal dead area. The chip is designed to read out a sensor of 320 x 320 pixels with dimensions of 75 {\mu}m x 75 {\mu}m or 160 x 160 pixels with dimensions of 150 {\mu}m x 150 {\mu}m. The readout architecture features energy binning of the single photons, which includes charge sharing correction for hits with energy spread over adjacent pixels. This paper presents the specifications, architecture, and circuit implementation of the chip, along with the first electrical measurements

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

The long term goal of the CERN Experimental Physics Department R&D on monolithic sensors is the development of sub-100nm CMOS sensors for high energy physics. The first technology selected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 included several small test chips with sensor and circuit prototypes and transistor test structures. One of the main questions to be addressed was how to optimize the sensor in the presence of significant in-pixel circuitry. In this paper this optimization is described as well as the experimental results from the MLR1 run confirming its effectiveness. A second submission investigating wafer-scale stitching has just been completed. This work has been carried out in strong synergy with the ITS3 upgrade of the ALICE experiment

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics

The long term goal of the CERN Experimental Physics Department R&D on monolithic sensors is the development of sub-100nm CMOS sensors for high energy physics. The first technology selected is the TPSCo 65nm CMOS imaging technology. A first submission MLR1 included several small test chips with sensor and circuit prototypes and transistor test structures. One of the main questions to be addressed was how to optimize the sensor in the presence of significant in-pixel circuitry. In this paper this optimization is described as well as the experimental results from the MLR1 run confirming its effectiveness. A second submission investigating wafer-scale stitching has just been completed. This work has been carried out in strong synergy with the ITS3 upgrade of the ALICE experiment

Forward-central two-particle correlations in p-Pb collisions at root s(NN)=5.02 TeV

Two-particle angular correlations between trigger particles in the forward pseudorapidity range (2.5 2GeV/c. (C) 2015 CERN for the benefit of the ALICE Collaboration. Published by Elsevier B. V.Peer reviewe