Space Charge at Nanoscale: Probing Injection and Dynamic Phenomena Under Dark/Light Configurations by Using KPFM and C-AFM

International audienc

Fabrication of Al:HfO2 Gate Dielectric MOSFETs

Replacing the traditional SiO2 gate oxide in a MOSFET with ferroelectric HfO2 creates a 1T memory device referred to as a FeFET. The bi-stable polarization states cause a retained threshold voltage shift known as the memory window. Ferroelectric HfO2 offers a number of material and electrical advantages over perovskite based ferroelectrics such as PZT or SBT. Due to its use as a high-k dielectric, the ALD capability and etch characteristics of hafnium oxide are well documented. Ferroelectric HfO2 has been shown to be thermally stable up to 1000 C, making gate first FeFET processes feasible. Electrically, HfO2 is capable of achieving much larger memory windows due to a high coercive field, on the order of 1-2 MV/cm. This property also allows for much thinner films (\u3c30 \u3enm) without degradation of the memory window, and the potential for finFET applications. This work focuses on the integration of aluminum doped HfO2 into a standard RIT FET process. Previous work at RIT has led to the development of an ALD recipe and subsequent anneal to induce the ferroelectric crystal phase in Al:HfO2. In this work, n-channel MOSFETs with aluminum gate/20nm Al:HfO2/p-Si have been de- signed and fabricated. Etching of Al:HfO2 has been investigated using chlorine based plasma etching. The devices show a subthreshold slope of 75 mV/dec. Pulse testing reveals significant threshold voltage shift due to electron charge trapping commonly observed in Hf based dielectrics. I-V characteristics show mobility degradation, which is caused by Coulomb scattering as a result of trapped charges. For the devices to exhibit ferroelectric behavior with high on-state current, measurement and mitigation of charge trapping need to be further investigated

The Direct Tunneling, Dielectric Breakdown Investigation, and RRAM Application in MBE Hexagonal Boron Nitride Monolayers Using Metal-Insulator-Metal Devices

In today’s post-Morre era, low-dimensional materials and their potential electronic applications have attracted extensive attention, but high-quality material synthesis and complicated device physics investigation is still challenging. Our lab is able to use Molecular Beam Epitaxy (MBE) epitaxy to reliably grow high quality millimeter grain size continuous ultrathin 2D (two-dimensional) hexagonal boron-nitridefilm (h-BN ) on Cobalt (Co) and Nickle (Ni) catalytic transition metal substrates. This is highly advantage in 2D electronic and photonic device applications. In this thesis, we report our comprehensive electric tunneling, dielectric breakdown, and memory application of single-layer h-BN film by fabricating scalable Metal-insulator-metal (MIM) diodes. Direct tunneling and dielectric breakdown in molecular beam epitaxial hexagonal boron nitride (h-BN) monolayers were studied based on Ni/h-BN/Ni device configuration in Chapter 2. Effective tunneling areas are orders of magnitude smaller than the physical areas of the devices. Statistical Weibull analysis of the breakdown characteristics shows that breakdown area-scaling law applies to the effective areas rather than physical areas of the devices. The h-BN based MIM devices can sustain repeated DC voltage sweeping stresses up to 85 times under an extremely high compliance current of 100 mA, and the critical electric field is determined to be at least 11.8 MV/cm, demonstrating high dielectric strength and reliability of these h-BN monolayers. The mechanism of the breakdown and recovery of the h-BN monolayer MIM devices is also discussed. The second project (Chapter 3) is devoted to the evaluation of Resistive Random Access Memory (RRAM) devices and the mechanism discussion of monolayer h-BN in MIM structure. The memory performance of bipolar switching shows great endurance with 97 cycles at 100mA compliance current, and a high average of 10^3 on/off ratio, but the reliability is an issue. For this particular film, both non-volatile bipolar and unipolar resistive switching (RS) and volatile threshold (TH) switching phenomena were found to coexist and could be converted from one to the other by controlling the electrical power, which provides a better understanding of the switching models. In devices with Graphene bottom electrodes, bipolar resistive switching with self-compliance current is discovered, making h-BN potential in low-power device applications

Multiscale modeling for application-oriented optimization of resistive random-access memory

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many dierent physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material's microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device's performance and variability to be evaluated, the analog resistance switching to be optimized, and the device's reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks

Modelling and characterization of the quantum dot floatiing gate flash memory

Master'sMASTER OF ENGINEERIN

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Built-In Test Engine For Memory Test

In this paper we will present an on-chip method for testing high performance memory devices, that occupies minimal area and retains full flexibility. This is achieved through microcode test instructions and the associated on-chip state machine. In addition, the proposed methodology will enable at-speed testing of memory devices. The relevancy of this work is placed in context with an introduction to memory testing and the techniques and algorithms generally used today

Towards Oxide Electronics:a Roadmap

At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore's law is approaching the insurmountable barrier given by the ultimate atomic nature of matter. A major challenge for 21st century scientists is finding novel strategies, concepts and materials for replacing silicon-based CMOS semiconductor technologies and guaranteeing a continued and steady technological progress in next decades. Among the materials classes candidate to contribute to this momentous challenge, oxide films and heterostructures are a particularly appealing hunting ground. The vastity, intended in pure chemical terms, of this class of compounds, the complexity of their correlated behaviour, and the wealth of functional properties they display, has already made these systems the subject of choice, worldwide, of a strongly networked, dynamic and interdisciplinary research community. Oxide science and technology has been the target of a wide four-year project, named Towards Oxide-Based Electronics (TO-BE), that has been recently running in Europe and has involved as participants several hundred scientists from 29 EU countries. In this review and perspective paper, published as a final deliverable of the TO-BE Action, the opportunities of oxides as future electronic materials for Information and Communication Technologies ICT and Energy are discussed. The paper is organized as a set of contributions, all selected and ordered as individual building blocks of a wider general scheme. After a brief preface by the editors and an introductory contribution, two sections follow. The first is mainly devoted to providing a perspective on the latest theoretical and experimental methods that are employed to investigate oxides and to produce oxide-based films, heterostructures and devices. In the second, all contributions are dedicated to different specific fields of applications of oxide thin films and heterostructures, in sectors as data storage and computing, optics and plasmonics, magnonics, energy conversion and harvesting, and power electronics

Electrical characterization and application of pulsed DC magnetron sputtered zirconium oxide

As aggressive scaling of CMOS circuits continues, gate oxide thickness is reduced in order to maintain control of ever shrinking channel lengths. Current cutting edge transistors are using a gate oxide thickness below 20Å, approaching a regime where direct, or quantum, tunneling is the primary leakage mechanism. Below ~16Å, leakage becomes too great for use in MOS transistors. There are short-term fixes in place, however the industry road map indicates the need for an alternative to SiO2 within five years. Among the leading candidates is Zirconium Oxide (ZrO2). ZrO2 was investigated as a possible replacement for Si02 in MOS devices. A statistically designed experiment was utilized to optimize processing parameters. MOS capacitors were used as a test vehicle. Leakage less than 200pA, breakdown strength greater than 8MV/cm, and relative permittivity greater than 7, have been demonstrated. ZrO2 gate dielectric, PMOS transistors have been fabricated with l-V characteristics comparable to transistors with a SiO2 gate dielectric, as shown in the l-V plot below. An initial investigation into a damascene Copper/Titanium gate stack, utilizing ZrO2 as a gate dielectric, was also been performed. Capacitors fabricated in this manner exhibited similar reliability results as capacitors fabricated using conventional processes. Graph: lDS vs. VDS at different VGS, for a PMOS transistor with a ZrO2 gate dielectric. Graph is difficult to read

Electrical Characterisation of Ferroelectric Field Effect Transistors based on Ferroelectric HfO2 Thin Films

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO2) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO2-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.:1 Introduction 2 Fundamentals 2.1 Non-volatile semiconductor memories 2.2 Emerging memory concepts 2.3 Ferroelectric memories 3 Characterisation methods 3.1 Memory characterisation tests 3.2 Ferroelectric memory specific characterisation tests 3.3 Trapping characterisation methods 3.4 Microstructural analyses 4 Sample description 4.1 Metal-insulator-metal capacitors 4.2 Ferroelectric field effect transistors 5 Stabilisation of the ferroelectric properties in Si:HfO2 thin films 5.1 Impact of the silicon doping 5.2 Impact of the post-metallisation anneal 5.3 Impact of the film thickness 5.4 Summary 6 Electrical properties of the ferroelectric Si:HfO2 thin films 6.1 Field cycling effect 6.2 Switching kinetics 6.3 Fatigue behaviour 6.4 Summary 7 Ferroelectric field effect transistors based on Si:HfO2 films 7.1 Effect of the silicon doping 7.2 Program and erase operation 7.3 Retention behaviour 7.4 Endurance properties 7.5 Impact of scaling on the device performance 7.6 Summary 8 Trapping effects in Si:HfO2-based FeFETs 8.1 Trapping kinetics of the bulk Si:HfO2 traps 8.2 Detrapping kinetics of the bulk Si:HfO2 traps 8.3 Impact of trapping on the FeFET performance 8.4 Modified approach for erase operation 8.5 Summary 9 Summary and Outloo