Creating a Healthy Home Environment for Good Nutrition

This is a brochure which gives tools to people who are trying to avoid dining out in order to improve their nutrition by eating at home. However, they need more information and guidance as to how to do this successfully. Obesity is not only a product of eating at restaurants outside of the house, but it is also caused by eating habits throughout the day at home, which stem from grocery shopping practices. The information provided creates awareness that well-intentioned home eating habits can still be damaging to health, and offer advice as to how somebody can set up their default home environment to facilitate healthier and more nutritious eating habits. In addition, tips are provided about how to stick to one’s shopping list of planned and healthy foods by creating awareness of advertising in grocery stores. It prompts customers into impulse purchasing foods they did not plan buy, which typically lack nutritional value and are higher in fat and sugars.https://dune.une.edu/an_studedres/1166/thumbnail.jp

High-Precision Pulse Generator

A document discusses a pulse generator with subnanosecond resolution implemented with a low-cost field-programmable gate array (FPGA) at low power levels. The method used exploits the fast carry chains of certain FPGAs. Prototypes have been built and tested in both Actel AX and Xilinx Virtex 4 technologies. In-flight calibration or control can be performed by using a similar and related technique as a time interval measurement circuit by measuring a period of the stable oscillator, as the delays through the fast carry chains will vary as a result of manufacturing variances as well as the result of environmental conditions (voltage, aging, temperature, and radiation)

Compact, Reliable EEPROM Controller

A compact, reliable controller for an electrically erasable, programmable read-only memory (EEPROM) has been developed specifically for a space-flight application. The design may be adaptable to other applications in which there are requirements for reliability in general and, in particular, for prevention of inadvertent writing of data in EEPROM cells. Inadvertent writes pose risks of loss of reliability in the original space-flight application and could pose such risks in other applications. Prior EEPROM controllers are large and complex and do not provide all reasonable protections (in many cases, few or no protections) against inadvertent writes. In contrast, the present controller provides several layers of protection against inadvertent writes. The controller also incorporates a write-time monitor, enabling determination of trends in the performance of an EEPROM through all phases of testing. The controller has been designed as an integral subsystem of a system that includes not only the controller and the controlled EEPROM aboard a spacecraft but also computers in a ground control station, relatively simple onboard support circuitry, and an onboard communication subsystem that utilizes the MIL-STD-1553B protocol. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD- 1553B is commonly used in defense and space applications.) The intent was to both maximize reliability while minimizing the size and complexity of onboard circuitry. In operation, control of the EEPROM is effected via the ground computers, the MIL-STD-1553B communication subsystem, and the onboard support circuitry, all of which, in combination, provide the multiple layers of protection against inadvertent writes. There is no controller software, unlike in many prior EEPROM controllers; software can be a major contributor to unreliability, particularly in fault situations such as the loss of power or brownouts. Protection is also provided by a powermonitoring circuit

Using Spare Logic Resources To Create Dynamic Test Points

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem

Determining Optimal Reliability Targets Through Analysis of Product Validation Cost and Field Warranty Data

This work develops a new methodology to minimize the life cycle cost of a product using the decision variables controlled by a reliability/quality professional during a product development process. This methodology incorporates all product dependability-related activities into a comprehensive probabilistic cost model that enables minimization of the product's life cycle cost using the product dependability control variables. The primary model inputs include the cost of ownership of test equipment, forecasted cost of warranty returns, and environmental test parameters of a product validation program. Among these parameters, an emphasis is placed upon test duration and test sample size for durability related environmental tests. The warranty forecasting model is based on data mining of past warranty claims, parametric probabilistic analysis of the existing field data, and a piecewise application of several statistical distributions. The modeling process is complicated by insufficient knowledge about the relationship between product quality and product reliability. This can be attributed to the lack of studies establishing the effect of product validation activities on future field failures, overall lack of comprehensive field failure studies, and the market's dictation of warranty terms as opposed to warranties based on engineering rationale. As a result of these complicating factors an innovative approach to estimating the quality-reliability relationship using probabilistic methods and stochastic simulation has been developed. The overall cost model and its minimization are generated using a Monte Carlo method that accounts for the propagation of uncertainties from the model inputs and their parameters to the life cycle cost solution. This research provides reliability and quality professionals with a methodology to evaluate the efficiency of a product validation program from a life cycle cost point of view and identifies ways to improve the validation test flow by adjusting test durations, sample sizes, and equipment utilization. Solutions balance a rigorous theoretical treatment and practical applications and are specifically applied to the electronics industry

Small Microprocessor for ASIC or FPGA Implementation

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz

The Design, Characterization, and Testing of the CRYO ASIC Front End Motherboard for the Deep Underground Neutrino Experiment

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Warranty Data Analysis: A Review

Warranty claims and supplementary data contain useful information about product quality and reliability. Analysing such data can therefore be of benefit to manufacturers in identifying early warnings of abnormalities in their products, providing useful information about failure modes to aid design modification, estimating product reliability for deciding on warranty policy and forecasting future warranty claims needed for preparing fiscal plans. In the last two decades, considerable research has been conducted in warranty data analysis (WDA) from several different perspectives. This article attempts to summarise and review the research and developments in WDA with emphasis on models, methods and applications. It concludes with a brief discussion on current practices and possible future trends in WDA