Design of Low Power Vedic Multiplier Based on Reversible Logic

Reversible logic is a new technique to reduce the power dissipation. There is no loss of information in reversible logic and produces unique output for specified inputs and vice-versa. There is no loss of bits so the power dissipation is reduced. In this paper new design for high speed, low power and area efficient 8-bit Vedic multiplier using Urdhva Tiryakbhyam Sutra (ancient methodology of Indian mathematics) is introduced and implemented using Reversible logic to generate products with low power dissipation. UT Sutra generates partial product and sum in single step with less number of adders unit when compare to conventional booth and array multipliers which will reduce the delay and area utilized, Reversible logic will reduce the power dissipation. An 8-bit Vedic multiplier is realized using a 4-bit Vedic multiplier and modified ripple carry adders. The proposed logic blocks are implemented using Verilog HDL programming language, simulation using Xilinx ISE software

Pipelined vedic multiplier with manifold adder complexity levels

Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay

A 4x4 Bit Vedic Multiplier with Different Voltage Supply in 90 nm CMOS Technology

In recent years, due to the rapid growth of high performance digital systems, speed and power consumption become very vital in multiplier design. In this paper, a 4x4 bit Vedic multiplier has been designed using the combination of Urdhva Triyakbyam Sutra and 13T hybrid full adder (HFA). This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which minimize the number of partial products compared to the conventional multiplication algorithm. The multiplier is simulated using Synopsys Custom Tools with General Process Design Kit (GPDK) of 90 nm CMOS technology using several voltage supplies to find the most optimum value for the voltage supply to be used. The result shows that with the usage of 1 V voltage supply, the new design of multiplier using a combination of HFA and Vedic mathematics is able to produce the lowest power consumption and least delay time. The 4x4 bit Vedic multiplier is able to yield a full output voltage swing with a power consumption of only 0.2015 mW, delay of 376 ps and compact area of 3100 µm2

A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps

IMPLEMENTATION OF AN EFFICIENT AND OPTIMIZED VEDIC MULTIPLIER DESIGN USING REVERSIBLE LOGIC GATES

Multiplier design is always a challenging task; however many   designs are proposed, the user needs demands much more optimized ones. Vedic mathematics provides   some   algorithms that evaluate fast results, both in mental calculations or hardware design. Power dissipation is continuously reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper the modified design increase the performance by maintain the design functionality without any degradation. The Total Reversible Logic Implementation Cost (TRLIC) evaluate the proposed design. This multiplier has application over  designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.

Urdhva Tiryagbhyam Sutra Multiplier Based 32-Bit MAC Design

The Vedic Multiplier and the Reversible Logic Gates has Designed and actualized in the increase and Accumulate Unit (MAC) and that is appeared in this paper. A Vedic multiplier is composed by utilizing Urdhava Triyagbhayam sutra and the snake configuration is finished by utilizing reversible rationale entryway. Reversible rationales are likewise the crucial necessity for the developing field of Quantum processing. The Vedic multiplier is utilized for the increase unit in order to decrease halfway items and to get elite and lesser territory .The reversible rationale is utilized to get less power. The MAC is composed in Verilog HDL and the recreation is done in Xilinx 14.2 and blend is done utilizing Xilinx. The chip outline for the proposed MAC is likewise completed

A collection of arithmetic exercises designed particularly for the superior child in grade three of four to supplement the standard program at those grade levels

Thesis (Ed.M.)--Boston Universit

Self-oscillation

Physicists are very familiar with forced and parametric resonance, but usually not with self-oscillation, a property of certain dynamical systems that gives rise to a great variety of vibrations, both useful and destructive. In a self-oscillator, the driving force is controlled by the oscillation itself so that it acts in phase with the velocity, causing a negative damping that feeds energy into the vibration: no external rate needs to be adjusted to the resonant frequency. The famous collapse of the Tacoma Narrows bridge in 1940, often attributed by introductory physics texts to forced resonance, was actually a self-oscillation, as was the swaying of the London Millennium Footbridge in 2000. Clocks are self-oscillators, as are bowed and wind musical instruments. The heart is a "relaxation oscillator," i.e., a non-sinusoidal self-oscillator whose period is determined by sudden, nonlinear switching at thresholds. We review the general criterion that determines whether a linear system can self-oscillate. We then describe the limiting cycles of the simplest nonlinear self-oscillators, as well as the ability of two or more coupled self-oscillators to become spontaneously synchronized ("entrained"). We characterize the operation of motors as self-oscillation and prove a theorem about their limit efficiency, of which Carnot's theorem for heat engines appears as a special case. We briefly discuss how self-oscillation applies to servomechanisms, Cepheid variable stars, lasers, and the macroeconomic business cycle, among other applications. Our emphasis throughout is on the energetics of self-oscillation, often neglected by the literature on nonlinear dynamical systems.Comment: 68 pages, 33 figures. v4: Typos fixed and other minor adjustments. To appear in Physics Report