Reversible logic is a new technique to reduce the power dissipation. There is no loss of information in reversible
logic and produces unique output for specified inputs and vice-versa. There is no loss of bits so the power
dissipation is reduced. In this paper new design for high speed, low power and area efficient 8-bit Vedic
multiplier using Urdhva Tiryakbhyam Sutra (ancient methodology of Indian mathematics) is introduced and
implemented using Reversible logic to generate products with low power dissipation. UT Sutra generates partial
product and sum in single step with less number of adders unit when compare to conventional booth and array
multipliers which will reduce the delay and area utilized, Reversible logic will reduce the power dissipation. An
8-bit Vedic multiplier is realized using a 4-bit Vedic multiplier and modified ripple carry adders. The proposed
logic blocks are implemented using Verilog HDL programming language, simulation using Xilinx ISE software
