Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

A DLL Based Test Solution for 3D ICs

Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations have obvious advantages over the conventional two dimensional IC implementations in performance, capacity, and power consumption. A passive Si interposer utilizing Through-Silicon via (TSV) technology is used for 2.5D IC integration. TSV is also the enabling technology for 3D IC integration. TSV manufacturing defects can affect the performance of stacked devices and reduce the yield. Manufacturing test methodologies for TSVs have to be developed to ensure fault-free devices. This thesis presents two test methods for TSVs in 2.5D and 3D ICs utilizing Delay-Locked Loop (DLL) modules. In the test method developed for TSVs in 2.5D ICs, a DLL is used to determine the propagation delay for fault detection. TSV faults in 3D ICs are detected through observation of the control voltage of a DLL. The proposed test methods present a robust performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLLs. 3D full-wave simulations are performed to extract circuit level models for TSVs and fragments of an interposer wires using HFSS simulation tools. The extracted TSV models are then used to perform circuit level simulations using ADS tools from Agilent. Simulation results indicate that the proposed test solution for TSVs can detect manufacturing defects affecting the TSV propagation delay

US Microelectronics Packaging Ecosystem: Challenges and Opportunities

The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technological solutions to enhance cost-effectiveness while incorporating more features into the silicon footprint. One promising approach is Heterogeneous Integration (HI), which involves advanced packaging techniques to integrate independently designed and manufactured components using the most suitable process technology. However, adopting HI introduces design and security challenges. To enable HI, research and development of advanced packaging is crucial. The existing research raises the possible security threats in the advanced packaging supply chain, as most of the Outsourced Semiconductor Assembly and Test (OSAT) facilities/vendors are offshore. To deal with the increasing demand for semiconductors and to ensure a secure semiconductor supply chain, there are sizable efforts from the United States (US) government to bring semiconductor fabrication facilities onshore. However, the US-based advanced packaging capabilities must also be ramped up to fully realize the vision of establishing a secure, efficient, resilient semiconductor supply chain. Our effort was motivated to identify the possible bottlenecks and weak links in the advanced packaging supply chain based in the US.Comment: 22 pages, 8 figure

Thermal performance enhancement of packaging substrates with integrated vapor chamber

The first part of this research investigates the effects of copper structures, such as copper through-package-vias (TPVs), and copper traces in redistribution layer (RDL), on the thermal performance of glass interposers through numerical and experimental approaches. Numerical parametric study on 2.5D interposers shows that as more copper structures are incorporated in glass interposers, the performance of silicon and glass interposers becomes closer, showing 31% difference in thermal resistance, compared to 53% difference without any copper structures in both interposers. In the second part of this study, a thermal model of glass interposer mounted on the vapor chamber integrated PCB is developed using multi-scale modeling scheme. The comparison of thermal performance between silicon and glass interposers shows that integration of vapor chamber with PCB makes thermal performance of both interposers almost identical, overcoming the limitation posed by low thermal conductivity of glass. The third part of this thesis focuses on design, fabrication, and performance measurement of PCB integrated with vapor chamber. Copper micropillar wick structure is fabricated on PCB with electroplating process, and its wettability is enhanced by silica nanoparticle coating. Design of the wick for the vapor chamber is determined based on the capillary performance and permeability test results. Fabricated device with ultra-thin thickness (~800 µm) shows higher thermal performance than copper plated PCB with the same thickness. Finally, 3D computational fluid dynamics/heat transfer model of the vapor chamber is developed, and modeling result is compared with test result.Ph.D

MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

Book of Knowledge (BOK) for NASA Electronic Packaging Roadmap

The objective of this document is to update the NASA roadmap on packaging technologies (initially released in 2007) and to present the current trends toward further reducing size and increasing functionality. Due to the breadth of work being performed in the area of microelectronics packaging, this report presents only a number of key packaging technologies detailed in three industry roadmaps for conventional microelectronics and a more recently introduced roadmap for organic and printed electronics applications. The topics for each category were down-selected by reviewing the 2012 reports of the International Technology Roadmap for Semiconductor (ITRS), the 2013 roadmap reports of the International Electronics Manufacturing Initiative (iNEMI), the 2013 roadmap of association connecting electronics industry (IPC), the Organic Printed Electronics Association (OE-A). The report also summarizes the results of numerous articles and websites specifically discussing the trends in microelectronics packaging technologies

Integrated silicon photonic packaging

Silicon photonics has garnered plenty of interests from both the academia and industry due to its high-speed transmission potential as well as sensing capability to complement silicon electronics. This has led to significant growth on the former, valuing at US$626.8M in 2017 and is expected to grow 3-fold to US$ 1,988.2M by 2023, based on data from MarketsandMarkets™. Silicon photonics’ huge potential has led to worldwide attention on fundamental research, photonic circuit designs and device fabrication technologies. However, as with silicon electronics in its early years, the silicon photonics industry today is extremely fragmented with various chip designs and layouts. Most silicon photonic devices fabricated are not able to reach the hand of consumers, due to a lack of information related to packaging design rules, components and processes. The importance of packaging technologies, which play a crucial role in turning photonic circuits and devices into the final product that end users can used in their daily lives, has been overlooked and understudied. This thesis aims to – 1. fill the missing gap by adapting existing electronics packaging techniques, 2. assess its scalability, 3. assess supply chain integration and finally 4. develop unique packaging approaches specifically for silicon photonics. The first section focused on high density packaging components and processes using University of California, Berkeley’s state-of-the-art silicon photonic MEMS optical switches as test devices. Three test vehicles were developed using (1) via-less ceramic and (2) spring-contacted electrical interposers for 2D integration and (3) through-glass-via electrical interposers for 2.5D heterogeneous integration. A high density (1) lidless fibre array and (2) a 2D optical interposer, which allows pitch-reduction of optical waveguides were also developed in this thesis. Together, these components demonstrated the world’s first silicon 2 photonic MEMS optical switch package and subsequently the highest density silicon photonic packaging components with 512 electrical I/Os and 272 optical I/Os. The second section then moved away from active optical coupling that was used in the former, investigating instead passive optical packaging concepts for the future. Two approaches were investigated - (1) grating-to-grating and (2) evanescent couplings. The former allows the development of pluggable packages, separating fibre coupling away from the device while the latter allows simultaneous optical and electrical packaging on a glass wafer in a single process. Lastly, the knowhow and concepts developed in this thesis were compiled into packaging design rules and subsequently introduced into H2020-MORPHIC, PIXAPP packaging training courses (as a trainer) and other packaging projects within the group

Compliant copper microwire arrays for reliable interconnections between large low-CTE packages and printed wiring board

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.Ph.D

Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits

Title from PDF of title page viewed August 28, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 120-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016Floating gate transistor is the basic building block of non-volatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene nanotechnology. In this paper we present a new floating gate transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In the proposed graphene based floating gate transistor (GFGT) a multilayer structure of graphene nanoribbon (GNR) would be used as the channel of the field effect transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed an analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. Based on our analysis we have observed that proposed graphene based floating gate transistor could be operated at a reduced voltage compared to conventional silicon based floating gate devices. We have presented detail analysis of the operation and the programming and erasing processes of the proposed FGT, dependency of the programming and erasing current density on different parameters, impact of scaling the thicknesses of the control and tunneling oxides. These analyses are done based on the equivalent capacitance model of the device. We have analyze the programming and erasing by the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the mechanism of programming current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that programming is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide. With the growing demand for nonvolatile flash memory devices and increasing limitations of silicon technologies, there has been a growing interest to develop emerging flash memory by using alternative nanotechnology. The proposed FGT device for nonvolatile flash memory contains an MLGNR channel and a CNT floating gate with SiO₂ as the tunnel oxide. In this paper, we have presented detail analysis of the electrical properties and performance characteristics of the proposed FGT device. We have focused on the following aspects: current voltage (I-V) characteristics, threshold voltage variation (∆VTH), programming, erasing and reading power consumptions compared to the existing FGTs, and layer-by-layer current voltage characteristics comparison of the proposed GFGT device. To realize graphene field effect transistor (GFET), a general model is developed, validated and analyzed. This model is also used to estimate graphene channel behavior of the proposed GFGT. Reliability is the major concern of the Flash memory technology. We have analyzed retention characteristics of the proposed GFGT. We also have developed a radiation harness test model for the Si-FGT by using VTH variation principle due to the radiation exposure. Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this research, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model. Molybdenum disulfide (MoS2) based field effect transistor is considered as one of the promising future logic devices. Many other nanoelectronic devices based on MoS2 are currently under investigation. However, the challenge of providing reliable and efficient contact between 2D materials like MoS2 and the metal is still unresolved. The contact resistance between metal and MoS2 limits the application of MoS2 in current semiconductor technologies. In this paper, a detail analysis of metal-MoS2 contact has been presented. Specific contributions of this work are:investigation of the physical, material and electrical parameters that would determine the contact properties, analysis of the combined impact of the top and back gates for the first time, modeling of the crucial metal-MoS2 contact parameters, such as, sheet resistance (RSh), contact resistivity (ρc), contact resistance (RC) and transfer length (LT), investigation of the ways to incorporate the developed contact model into the electronic design automation (EDA) tools and investigation of different contact materials for the metal-MoS2 contact. The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law. To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an intermediate state. It is important to realize CAD design challenges of the 2.5D-IC/3D-IC when minimum spacing interconnects are used. The major contributions of this research work are as follows. Previously, for the small scale experimental purpose, small numbers (10-20) of TSVs, interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD solution is required to provide precise physical design and verification. Therefore, a solid CAD solution is provided here. Compatible with 40nm-technology design, which enables the Silicon Interposer to integrate with the digital, analog and RF dies together. Dimensions and spacing of the TSV and Bump are optimized by the 3D EM full wave field solver. To our best knowledge, at the interposer level, this design reports the most dense and well-defined RDL, TSV and micro-bump co-design on Silicon Interposer, which will be used for 2.5D-IC.Introduction and background -- Proposed Graphene Based Flash Memory -- Physical and Electrical Parameters of the Proposed Graphene Flash Memory Device -- Programming and Erasing Operation of the Proposed Graphene Flash Memory Device -- Reliability Analysis of the Proposed Graphene Flash Memory Device -- Radiation Hardness Analysis of the Floating Gate Transistor -- Benchmarking of the Proposed Graphene Flash Memory Device -- Graphene Field Effect Transistor (GFET) Generalized Model -- MoS2 FET Device and Contact Characterization and Modelling based on Modified Transfer Length Method (TLM) -- 2.5D Silicon Interposer Design in 40nm-Technology for 2D-IC and 3D-IC -- Conclusion and Future Wor