A Programmable Frequency Divider Having a Wide Division Ratio Range, and Close-to-50% Output Duty-Cycle

In Radio Frequency (RF) integrated circuit design field, programmable dividers are getting more and more attentions in recent years. A programmable frequency divider can divide an input frequency by programmable ratios [1]. It is a key component of a frequency synthesizer. It also can be used to generate variable clock-signals for: switched-capacitor filters (SCFs), digital systems with different power-states, as well as multiple clock-signals on the same system-on-a-chip (SOC). These circuits need high performance programmable frequency dividers, operating at high frequencies and having wide division ratio ranges, with binary division ratio controls and 50% output duty-cycle. Different types of programmable frequency dividers are reviewed and compared. A programmable frequency divider with a wide division ratio range of (8 ~ 524287) has been reported [2]. Because the output duty-cycle of this reported divider is far from 50%, the circuit in [2] has very limited applications. The proposed design solves this problem, without compromising other advantages of the design in [2]. The proposed design is fabricated in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. The duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant, with different input frequencies from GHz down to kHz ranges, with different temperatures and power supply voltages. This thesis provides an explanation of the design details and test results. A Phase Locked-Loop (PLL) based frequency synthesizer can generate different output frequencies. A programmable frequency divider is an important component of this type of PLL. Since bandwidth is expensive, it is preferred to reduce the frequency channel distance of a frequency synthesizer. Using a fractional programmable divider, the frequency channel distance of a PLL can be reduced, without reducing the reference frequency or increasing the settling time of the PLL. A frequency synthesizer with a programmable fractional divider is designed and fabricated. A brief description of the PLL design and test results are presented in this dissertation

Search for Nanosecond Near-infrared Transients around 1280 Celestial Objects

Stars and planetary system

Design, Analysis and Implementation of DLL clock generator

In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock generator circuits. In this work a DLL has been proposed the design uses dynamic phase detector (PD) for phase detection. Voltage controlled delay line (VCDL) of proposed DLL consists of twelve delay elements. Current starved inverters have been used as delay element. In this paper, a proposed duty cycle corrector solves the problem of the sensitivity to half transparent (HT) architecture and the stuck locking error in the DLL simultaneously proposed DLL is designed to work at an input frequency of 250MHz. The design also generates an output of 3GHz using a frequency multiplication block. The design uses 180nm CMOS process technology and consumes 1.88mW of power at 1.8V

A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved

[[sponsorship]]Test Technology Technical Council (TTTC), IEEE Computer Society ; Faculty of Information Technology, Brno University of Technology[[conferencetype]]國際[[conferencedate]]20130408~20130410[[booktype]]電子版[[iscallforpapers]]Y[[conferencelocation]]Karlovy Vary (Carlsbad), Czech Republi

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system

Panoramic optical and near-infrared SETI instrument: overall specifications and science program

We present overall specifications and science goals for a new optical and near-infrared (350 - 1650 nm) instrument designed to greatly enlarge the current Search for Extraterrestrial Intelligence (SETI) phase space. The Pulsed All-sky Near-infrared Optical SETI (PANOSETI) observatory will be a dedicated SETI facility that aims to increase sky area searched, wavelengths covered, number of stellar systems observed, and duration of time monitored. This observatory will offer an "all-observable-sky" optical and wide-field near-infrared pulsed technosignature and astrophysical transient search that is capable of surveying the entire northern hemisphere. The final implemented experiment will search for transient pulsed signals occurring between nanosecond to second time scales. The optical component will cover a solid angle 2.5 million times larger than current SETI targeted searches, while also increasing dwell time per source by a factor of 10,000. The PANOSETI instrument will be the first near-infrared wide-field SETI program ever conducted. The rapid technological advance of fast-response optical and near-infrared detector arrays (i.e., Multi-Pixel Photon Counting; MPPC) make this program now feasible. The PANOSETI instrument design uses innovative domes that house 100 Fresnel lenses, which will search concurrently over 8,000 square degrees for transient signals (see Maire et al. and Cosens et al., this conference). In this paper, we describe the overall instrumental specifications and science objectives for PANOSETI.Comment: 15 pages, 7 figures, 1 tabl

The Fluorescence Detector of the Pierre Auger Observatory

The Pierre Auger Observatory is a hybrid detector for ultra-high energy cosmic rays. It combines a surface array to measure secondary particles at ground level together with a fluorescence detector to measure the development of air showers in the atmosphere above the array. The fluorescence detector comprises 24 large telescopes specialized for measuring the nitrogen fluorescence caused by charged particles of cosmic ray air showers. In this paper we describe the components of the fluorescence detector including its optical system, the design of the camera, the electronics, and the systems for relative and absolute calibration. We also discuss the operation and the monitoring of the detector. Finally, we evaluate the detector performance and precision of shower reconstructions.Comment: 53 pages. Submitted to Nuclear Instruments and Methods in Physics Research Section

The Zwicky Transient Facility Observing System

The Zwicky Transient Facility (ZTF) is a synoptic optical survey for high-cadence time-domain astronomy. Building upon the experience and infrastructure of the highly successful Palomar Transient Factory (PTF) team, ZTF will survey more than an order of magnitude faster than PTF in sky area and volume in order to identify rare, rapidly varying optical sources. These sources will include a trove of supernovae, exotic explosive transients, unusual stellar variables, compact binaries, active galactic nuclei, and asteroids. The single-visit depth of 20.4 mag is well matched to spectroscopic follow-up observations, while the co-added images will provide wide sky coverage 1.5 – 2 mag deeper than SDSS. The ZTF survey will cover the entire Northern Sky and revisit fields on timescales of a few hours, providing hundreds of visits per field each year, an unprecedented cadence, as required to detect fast transients and variability. This high-cadence survey is enabled by an observing system based on a new camera having 47 deg^2 field of view – a factor of 6.5 greater than the existing PTF camera - equipped with fast readout electronics, a large, fast exposure shutter, faster telescope and dome drives, and various measures to optimize delivered image quality. Our project has already received an initial procurement of e2v wafer-scale CCDs and we are currently fabricating the camera cryostat. International partners and the NSF committed funds in June 2014 so construction can proceed as planned to commence engineering commissioning in 2016 and begin operations in 2017. Public release will allow broad utilization of these data by the US astronomical community. ZTF will also promote the development of transient and variable science methods in preparation for the seminal first light of LSST