Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications

This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD) PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration. In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation. The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches: • Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory. • Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA. In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership. The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version

Analysis and design of a wide dynamic range pulse-frequency modulation CMOS image sensor

Complementary Metal-Oxide Semiconductor (CMOS) image sensor is the dominant electronic imaging device in many application fields, including the mobile or portable devices, teleconference cameras, surveillance and medical imaging sensors. Wide dynamic range (WDR) imaging is of interest particular, demonstrating a large-contrast imaging range of the sensor. As of today, different approaches have been presented to provide solutions for this purpose, but there exists various trade-offs among these designs, which limit the number of applications. A pulse-frequency modulation (PFM) pixel offers the possibility to outperform existing designs in WDR imaging applications, however issues such as uniformity and cost have to be carefully handled to make it practical for different purposes. In addition, a complete evaluation of the sensor performance has to be executed prior to fabrication in silicon technology. A thorough investigation of WDR image sensor based on the PFM pixel is performed in this thesis. Starting with the analysis, modeling, and measurements of a PFM pixel, the details of every particular circuit operation are presented. The causes of dynamic range (DR) limitations and signal nonlinearity are identified, and noise measurement is also performed, to guide future design strategies. We present the design of an innovative double-delta compensating (DDC) technique which increases the sensor uniformity as well as DR. This technique achieves performance optimization of the PFM pixel with a minimal cost an improved linearity, and is carefully simulated to demonstrate its feasibility. A quad-sampling technique is also presented with the cooperation of pixel and column circuits to generate a WDR image sensor with a reduced cost for the pixel. This method, which is verified through the field-programmable gate array (FPGA) implementation, saves considerable area in the pixel and employs the maximal DR that a PFM pixel provides. A complete WDR image sensor structure is proposed to evaluate the performance and feasibility of fabrication in silicon technology. The plans of future work and possible improvements are also presented

Pixel design and characterization of high-performance tandem OLED microdisplays

Organic Light-Emitting Diode (OLED) microdisplays - miniature Electronic Displays comprising a sandwich of organic light emitting diode over a substrate containing CMOS circuits designed to function as an active matrix backplane – were first reported in the 1990s and, since then, have advanced to the mainstream. The smaller dimensions and higher performance of CMOS circuit elements compared to that of equivalent thin film transistors implemented in technologies for large OLED display panels offer a distinct advantage for ultra-miniature display screens. Conventional OLED has suffered from lifetime degradation at high brightness and high current density. Recently, tandem-structure OLED devices have been developed using charge generation layers to implement two or more OLED units in a single stack. They can achieve higher brightness at a given current density. The combination of emissive-nature, fast response, medium to high luminance, low power consumption and appropriate lifetime makes OLED a favoured candidate for near-to-eye systems. However, it is also challenging to evaluate the pixel level optical response of OLED microdisplays as the pixel pitch is extremely small and relative low light output per pixel. Advanced CMOS Single Photon Avalanche Diode (SPAD) technology is progressing rapidly and is being deployed in a wide range of applications. It is also suggested as a replacement for photomultiplier tube (PMT) for photonic experiments that require high sensitivity. CMOS SPAD is a potential tool for better and cheaper display optical characterizations. In order to incorporate the novel tandem structure OLED within the computer aided design (CAD) flow of microdisplays, we have developed an equivalent circuit model that accurately describes the tandem OLED electrical characteristics. Specifically, new analogue pulse width modulation (PWM) pixel circuit designs have been implemented and fabricated in small arrays for test and characterization purposes. We report on the design and characterization of these novel pixel drive circuits for OLED microdisplays. Our drive circuits are designed to allow a state-of-the-art sub-pixel pitch of around 5 μm and implemented in 130 nm CMOS. A performance comparison with a previous published analogue PWM pixel is reported. Moreover, we have employed CMOS SPAD sensors to perform detailed optical measurements on the OLED microdisplay pixels at very high sampling rate (50 kHz, 10 μs exposure), very low light level (2×10-4 cd/m2) and over a very wide dynamic range (83 dB) of luminance. This offers a clear demonstration of the potential of the CMOS SPAD technology to reveal hitherto obscure details of the optical characteristics of individual and groups of OLED pixels and thereby in display metrology in general. In summary, there are three key contributions to knowledge reported in this thesis. The first is a new equivalent circuit model specifically for tandem structure OLED. The model is verified to provide accurately illustrate the electrical response of the tandem OLED with different materials. The second is the novel analogue PWM pixel achieve a 5μm sub-pixel pitch with 2.4 % pixel-to-pixel variation. The third is the new application and successful characterization experiment of OLED microdisplay pixels with SPAD sensors. It revealed the OLED pixel overshoot behaviour with a QIS SPAD sensor

CMOS image sensor with bi-directional column sensor

CMOS image sensors have been around since the 1960\u27s. However due to poor light sensitivity and poor signal-to-noise ratios (SNR) the architecture was not popular. Since then many improvements have been made to the architecture, making camera designs that use CMOS imagers more prevalent. Much of the improvement in SNR has been due to fixed-pattern noise reduction. Correlated double sampling (CDS) is a popular technique to reduce the effects of this source of noise. The circuitry required to implement CDS can be complex and hinders other areas of an image sensor performance in some schemes. This thesis proposes a new technique that attenuates noise due to DC offset without the use of CDS. Beginning with a standard three transistor-per-pixel architecture, this thesis builds on previous CMOS image sensor designs and creates a new bi-directional amplifier architecture that eliminates DC offset due to transistor mismatch without the use of CDS. The architecture uses a single differential amplifier to both reset and readout the pixel. Simulations show that SNR range of the proposed column sensor is 48.71 - 44.63 dB, whereas an Active Column Sensor without CDS has an SNR of 31.88 - 28.78 dB under the same conditions. Using the proposed column sensor, a layout (TSMC 0.35um) for a small 4X4 pixel image sensor was designed and prototyped which proves that the bi-directional amplifier can be used as a column sensor. The proposed prototype shows the viability of the architecture for a future production camera. The simulated result for the image sensor show that it can be reset in 200 ns read out in 3.4us and has an overall size of 107.9X118.1 um2

Smart Sensor Networks For Sensor-Neural Interface

One in every fifty Americans suffers from paralysis, and approximately 23% of paralysis cases are caused by spinal cord injury. To help the spinal cord injured gain functionality of their paralyzed or lost body parts, a sensor-neural-actuator system is commonly used. The system includes: 1) sensor nodes, 2) a central control unit, 3) the neural-computer interface and 4) actuators. This thesis focuses on a sensor-neural interface and presents the research related to circuits for the sensor-neural interface. In Chapter 2, three sensor designs are discussed, including a compressive sampling image sensor, an optical force sensor and a passive scattering force sensor. Chapter 3 discusses the design of the analog front-end circuit for the wireless sensor network system. A low-noise low-power analog front-end circuit in 0.5μm CMOS technology, a 12-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS process and a 6-bit asynchronous level-crossing ADC realized in 0.18μm CMOS process are presented. Chapter 4 shows the design of a low-power impulse-radio ultra-wide-band (IR-UWB) transceiver (TRx) that operates at a data rate of up to 10Mbps, with a power consumption of 4.9pJ/bit transmitted for the transmitter and 1.12nJ/bit received for the receiver. In Chapter 5, a wireless fully event-driven electrogoniometer is presented. The electrogoniometer is implemented using a pair of ultra-wide band (UWB) wireless smart sensor nodes interfacing with low power 3-axis accelerometers. The two smart sensor nodes are configured into a master node and a slave node, respectively. An experimental scenario data analysis shows higher than 90% reduction of the total data throughput using the proposed fully event-driven electrogoniometer to measure joint angle movements when compared with a synchronous Nyquist-rate sampling system. The main contribution of this thesis includes: 1) the sensor designs that emphasize power efficiency and data throughput efficiency; 2) the fully event-driven wireless sensor network system design that minimizes data throughput and optimizes power consumption

Review on X-ray detectors based on scintillators and CMOS technology

This article describes the theoretical basis, design and implementation of X-ray microdetectors based on scintillating materials and CMOS technology. The working principle of such microdetectors consists in the absorption of X-rays by scintillators, which produce visible light. The visible light is then detected and converted into electric signals by means of photodetectors. In order to understand such detectors, several issues related to its implementation are presented in this article, namely: Production of X-rays and interaction between them and matter - the first step necessary to the detection of X-rays is that they must be absorbed by some material, in this case by a scintillator; Radiation detectors - there are several types of detectors, namely: pn junctions, photoconductors, based on thermal effects and scintillators; Fabrication of scintillator arrays - after the X-ray radiation is absorbed by a scintillator, this material emits visible light whose intensity is proportional to the total energy of the absorbed X-rays; Optical interfaces between scintillators and photodetectors - the visible light generated by scintillators must arrive to the photodetectors, so, it is necessary to have an interface between the scintillators and the photodetectors that ideally does not introduce losses; Photodetectors and interface electronics - the visible light is absorbed by the photodetectors and converted into electrical signals, which are finally converted into digital images by means of interface electronics. The article presents some promising patents on X-ray detectors based on scintillators and CMOS technology.Fundação para a Ciência e a Tecnologia (FCT) - Bolsa SFRH/BSAB/1014/201

DESIGN OF SMART SENSORS FOR DETECTION OF PHYSICAL QUANTITIES

Microsystems and integrated smart sensors represent a flourishing business thanks to the manifold benefits of these devices with respect to their respective macroscopic counterparts. Miniaturization to micrometric scale is a turning point to obtain high sensitive and reliable devices with enhanced spatial and temporal resolution. Power consumption compatible with battery operated systems, and reduced cost per device are also pivotal for their success. All these characteristics make investigation on this filed very active nowadays. This thesis work is focused on two main themes: (i) design and development of a single chip smart flow-meter; (ii) design and development of readout interfaces for capacitive micro-electro-mechanical-systems (MEMS) based on capacitance to pulse width modulation conversion. High sensitivity integrated smart sensors for detecting very small flow rates of both gases and liquids aiming to fulfil emerging demands for this kind of devices in the industrial to environmental and medical applications. On the other hand, the prototyping of such sensor is a multidisciplinary activity involving the study of thermal and fluid dynamic phenomenon that have to be considered to obtain a correct design. Design, assisted by finite elements CAD tools, and fabrication of the sensing structures using features of a standard CMOS process is discussed in the first chapter. The packaging of fluidic sensors issue is also illustrated as it has a great importance on the overall sensor performances. The package is charged to allow optimal interaction between fluids and the sensors and protecting the latter from the external environment. As miniaturized structures allows a great spatial resolution, it is extremely challenging to fabricate low cost packages for multiple flow rate measurements on the same chip. As a final point, a compact anemometer prototype, usable for wireless sensor network nodes, is described. The design of the full custom circuitry for signal extraction and conditioning is coped in the second chapter, where insights into the design methods are given for analog basic building blocks such as amplifiers, transconductors, filters, multipliers, current drivers. A big effort has been put to find reusable design guidelines and trade-offs applicable to different design cases. This kind of rational design enabled the implementation of complex and flexible functionalities making the interface circuits able to interact both with on chip sensors and external sensors. In the third chapter, the chip floor-plan designed in the STMicroelectronics BCD6s process of the entire smart flow sensor formed by the sensing structures and the readout electronics is presented. Some preliminary tests are also covered here. Finally design and implementation of very low power interfaces for typical MEMS capacitive sensors (accelerometers, gyroscopes, pressure sensors, angular displacement and chemical species sensors) is discussed. Very original circuital topologies, based on chopper modulation technique, will be illustrated. A prototype, designed within a joint research activity is presented. Measured performances spurred the investigation of new techniques to enhance precision and accuracy capabilities of the interface. A brief introduction to the design of active pixel sensors interface for hybrid CMOS imagers is sketched in the appendix as a preliminary study done during an internship in the CNM-IMB institute of Barcelona

CMOS digital pixel sensor array with time domain analogue to digital conversion

This thesis presents a digital pixel sensor array, which is the first stage of an ongoing project to produce a CMOS image sensor with on-chip image processing. The analogue to digital conversion is performed at the pixel level, with the result stored in pixel memory. This architecture allows fast, reliable access to the image data and simplifies the integration of the image array and the processing logic. Each pixel contains a photodiode sensor, a comparator, memory and addressing logic. The photodiode sensor operates in integrating mode, where the photodiode junction capacitance is first charged to an initial voltage, and then discharged by the photodiode leakage current, which is comprised mainly of optically generated carriers. The analogue to digital conversion is performed by measuring the time taken for the photodiode cathode voltage to fall from its initial voltage, to the comparator reference voltage. This triggers the 8-bit pixel memory, which stores a data value representative of the time. The trigger signal also resets the photodiode, which conserves the charge stored in the junction capacitance, and also prevents blooming. An on-chip control circuit generates the digital data that is distributed globally to the array. The control circuit compensates for the inverse relationship between the integration time and the photocurrent by adjusting the data clock timing. The period of the data clock is increased at the same rate as the integration time, resulting in a linear relationship between the digital data and the photocurrent. The design is realised as a 64 x 64 pixel array, manufactured in O.35µm 3.3 V CMOS technology. Each pixel occupies an area of 45µm x 45µm with a 12.3% fill factor, and the entire pixel array and control circuit measures 3.7mm x 3.9mm. Experimental results confirm the operation of the digital pixel, and the linearising control circuit. The digital pixel has a dynamic range of 85dB, and can be adapted to different lighting conditions by varying a single clock frequency. The data captured by the array can be randomly accessed, and is read from the array nondestructivcly

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses, including, among others, industrial, automotive, and medical equipment. The impressive growth in photodetector applications is closely linked to the development of CMOS technology, which now offers inexpensive and efficient analog and digi-tal signal processing capabilities. Detectors are often integrated with their respective front end and application-specific digital circuit on the same silicon die, forming complete systems on chip. In some cases the detector itself is not on the same chip but often part of the same package. However, this trend of co-integration of analog front end and digital circuits complicates the design of the analog part. The ever-decreasing supply voltage and the smaller transistors in advanced processes (which are driven by the development of digital cir-cuits) negatively impact the performance of the analog structures and complicates their design. For photodetector systems, the effect most importantly translates into a degradation of dynamic range and signal-to-noise ratio. One way to circumvent the problem of low supply voltages is to shift the operation from voltage domain to time domain. By doing so, the signal is no longer constrained by the supply rails and analog amplification is avoided. The signal takes the form of a time-based modulation, such as pulse-width modulation or pulse-frequency modulation. Another advantage is that the output signal of a time-domain photodetection system is directly interfaceable with digital circuits. In this work, a new type of CMOS-compatible photodetector displaying intrinsic light-to-time conversion is proposed. Its physical structure consists of a MOS gate interleaved with a PN junction. The MOS structure is acting as a photogate. The depletion region shrinks when photogenerated carriers fill the potential well. At some point, the anode of the PN structure is de-isolated from the rest of the detector and triggers a positive-feedback effect that leads to a very steep current increase through the PN-junction. This translates into a signal of very high amplitude and independent from light-intensity, which can be almost directly interfaced with digital circuits. This simplifies the front end circuit compared to photodiode-based systems. The physical behavior of the device is analyzed with the help of TCAD simulations and simple behavioral and shot-noise models are proposed. The device has been co-integrated with its driver and front end circuit in a standard CMOS process and its characteristics have been measured with a custom-made measurement system. The effect of bias parameters on the performance of the sensor are also analyzed. The limitations of the device are discussed, the most important ones being dark current and linearity. Techno-logical solutions, such as the implementation of the detector on Silicon-on-Insulator technology, are proposed to overcome the limitations. Finally, some application demonstrators have been realized. Other applications that could benefit from the detector are suggested, such as digital applications taking advantage of the latching behavior of the device, and a Photoplethysmography (PPG) system that uses a PLL-based control loop to minimize the emitting LED-current

Digital CMOS ISFET architectures and algorithmic methods for point-of-care diagnostics

Over the past decade, the surge of infectious diseases outbreaks across the globe is redefining how healthcare is provided and delivered to patients, with a clear trend towards distributed diagnosis at the Point-of-Care (PoC). In this context, Ion-Sensitive Field Effect Transistors (ISFETs) fabricated on standard CMOS technology have emerged as a promising solution to achieve a precise, deliverable and inexpensive platform that could be deployed worldwide to provide a rapid diagnosis of infectious diseases. This thesis presents advancements for the future of ISFET-based PoC diagnostic platforms, proposing and implementing a set of hardware and software methodologies to overcome its main challenges and enhance its sensing capabilities. The first part of this thesis focuses on novel hardware architectures that enable direct integration with computational capabilities while providing pixel programmability and adaptability required to overcome pressing challenges on ISFET-based PoC platforms. This section explores oscillator-based ISFET architectures, a set of sensing front-ends that encodes the chemical information on the duty cycle of a PWM signal. Two initial architectures are proposed and fabricated in AMS 0.35um, confirming multiple degrees of programmability and potential for multi-sensing. One of these architectures is optimised to create a dual-sensing pixel capable of sensing both temperature and chemical information on the same spatial point while modulating this information simultaneously on a single waveform. This dual-sensing capability, verified in silico using TSMC 0.18um process, is vital for DNA-based diagnosis where protocols such as LAMP or PCR require precise thermal control. The COVID-19 pandemic highlighted the need for a deliverable diagnosis that perform nucleic acid amplification tests at the PoC, requiring minimal footprint by integrating sensing and computational capabilities. In response to this challenge, a paradigm shift is proposed, advocating for integrating all elements of the portable diagnostic platform under a single piece of silicon, realising a ``Diagnosis-on-a-Chip". This approach is enabled by a novel Digital ISFET Pixel that integrates both ADC and memory with sensing elements on each pixel, enhancing its parallelism. Furthermore, this architecture removes the need for external instrumentation or memories and facilitates its integration with computational capabilities on-chip, such as the proposed ARM Cortex M3 system. These computational capabilities need to be complemented with software methods that enable sensing enhancement and new applications using ISFET arrays. The second part of this thesis is devoted to these methods. Leveraging the programmability capabilities available on oscillator-based architectures, various digital signal processing algorithms are implemented to overcome the most urgent ISFET non-idealities, such as trapped charge, drift and chemical noise. These methods enable fast trapped charge cancellation and enhanced dynamic range through real-time drift compensation, achieving over 36 hours of continuous monitoring without pixel saturation. Furthermore, the recent development of data-driven models and software methods open a wide range of opportunities for ISFET sensing and beyond. In the last section of this thesis, two examples of these opportunities are explored: the optimisation of image compression algorithms on chemical images generated by an ultra-high frame-rate ISFET array; and a proposed paradigm shift on surface Electromyography (sEMG) signals, moving from data-harvesting to information-focused sensing. These examples represent an initial step forward on a journey towards a new generation of miniaturised, precise and efficient sensors for PoC diagnostics.Open Acces