21 research outputs found

    Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade

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    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.Comment: 9 pages, 9 figures, TWEPP 2015 Conference, submitted to JINS

    High-Voltage CMOS Active Pixel Sensor

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    International audienceThe high-voltage CMOS (HVCMOS) sensors are a novel type of CMOS active pixel sensors for ionizing particles that can be implemented in CMOS processes with deep n-well option. The pixel contains one sensor electrode formed with a deep n-well implanted in a p-type substrate. CMOS pixel electronics, embedded in shallow wells, are placed inside the deep n-well. By biasing the substrate with a high negative voltage and by the use of a lowly doped substrate, a depleted region depth of at least 30 ÎŒm can be achieved. The electrons generated by a particle are collected by drift, which induces fast detectable signals. This publication presents a 4.2-cm 2 large HVCMOS pixel sensor implemented in a commercial 180-nm process on a lowly doped substrate and its characterization

    CMS physics technical design report : Addendum on high density QCD with heavy ions

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    CMOS pixel sensors on high resistive substrate for high-rate, high-radiation environments

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    In Press, Corrected Proof — Note to usersInternational audienceA depleted CMOS active pixel sensor (DMAPS) has been developed on a substrate with high resistivity in a high voltage process. High radiation tolerance and high time resolution can be expected because of the charge collection by drift. A prototype of DMAPS was fabricated in a 150 nm process by LFoundry. Two variants of the pixel layout were tested, and the measured depletion depths of the variants are 166 ÎŒm and 80 ÎŒm. We report the results obtained with the prototype fabricated in this technology

    Design of a HVCMOS pixel sensor ASIC with on-chip readout electronics for ATLAS ITk Upgrade

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    International audienceATLASpix is a series of monolithic High Voltage CMOS (HVCMOS) sensor chips that are engineered to meet the requirements of outer layers of ATLAS ITk pixel tracker for HL-LHC upgrade. They are large collection electrode designs on high resistive wafers to ensure high detection efficiency and radiation tolerance. The readout electronics are placed on the chip periphery. ATLASpix1_M2 prototype is fabricated in a commercial 180 nm CMOS technology and has an active area of 1.6 cm × 0.33 cm. No clock signals are propagated inside the pixel matrix reducing the crosstalk and helping to achieve an estimated power consumption of 300 mW/cm2^2. This work presents the design of ATLASpix_M2 with emphasis on its readout electronics, together with some experimental results

    Depleted fully monolithic active CMOS pixel sensors (DMAPS) in high resistivity 150 nm technology for LHC

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    International audienceDepleted monolithic CMOS 1 1 Complementary metal-oxide-semiconductor.  active pixel sensors (DMAPS) have been developed to demonstrate their suitability as pixel detectors in the outer layers of the ATLAS Inner Tracker (ITk) pixel detector in the High-Luminosity Large Hadron Collider (HL-LHC). Two prototypes have been fabricated using a 150 nm CMOS technology on high resistivity ( ≄  2 k Ω cm) wafers. The chip size of 10 mm  ×  10 mm is similar to that of the current FE-I3 ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and analog front end circuitry of the DMAPS. The other one is a fully monolithic DMAPS, including fast readout digital logics that handle the required hit rate. To yield a strong homogeneous electric field within the sensor volume, back-side process of the wafer was tested. The prototypes were irradiated with X-rays up to a total ionization dose (TID) of 50 Mrad(SiO 2 ) and with neutrons up to a 1 MeV neutron equivalent fluence of 10 15  n eq /cm 2 to test non-ionizing energy loss (NIEL) effects. The analog front end circuitry maintained its performance after TID irradiation, and the hit efficiency at < 10 −7 noise occupancy was as high as 98.9% after NIEL irradiation

    Test results of irradiated CMOS pixel circuits in 150 nm CMOS technology for the ATLAS Inner Tracker Upgrade

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    International audienceA major upgrade for the ATLAS Inner Tracker at the Large Hadron Collider (LHC) is scheduled in 2026. Depleted CMOS pixel sensors on high resistivity substrates in LFoundry 150 nm technology are an interesting option for this upgrade. Recently two large demonstrators, one based on a hybrid concept called LF-CPIX and the other based on a fully monolithic concept called LF-Monopix have been produced. Both prototypes were characterized in the lab and after irradiation up to 160 MRad under CERN’s 24 GeV Proton Synchrotron beam. In this work, we will describe the behavior under radiation of the two prototypes

    Development of depleted monolithic pixel sensors in 150 nm CMOS technology for the ATLAS Inner Tracker upgrade

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    International audienceThis work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described followed by the simulation and measurement results
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