Exploiting Partial Symmetries for Markov Chain Aggregation

International audience; The technique presented in this paper allows the automatic construction of a lumped Markov chain for almost symmetrical Stochastic Well-formed Net (SWN) models. The starting point is the Extended Symbolic Reachability Graph (ESRG), which is a reduced representation of a SWN model reachability graph (RG), based on the aggregation of states into classes. These classes may be used as aggregates for lumping the Continuous Time Markov Chain (CTMC) isomorphic to the model RG: however it is not always true that the lumpability condition is verified by this partition of states. In the paper we propose an algorithm that progressively refines the ESRG classes until a lumped Markov chain is obtained

The GreatSPN tool: recent enhancements

GreatSPN is a tool that supports the design and the qualitative and quantitative analysis of Generalized Stochastic Petri Nets (GSPN) and of Stochastic Well-Formed Nets (SWN). The very first version of GreatSPN saw the light in the late eighties of last century: since then two main releases where developed and widely distributed to the research community: GreatSPN1.7 [13], and GreatSPN2.0 [8]. This paper reviews the main functionalities of GreatSPN2.0 and presents some recently added features that significantly enhance the efficacy of the tool

On the construction of stable project baseline schedules.

The vast majority of project scheduling efforts assume complete information about the scheduling problem to be solved and a static deterministic environment within which the pre-computed baseline schedule will be executed. In reality, however, project activities are subject to considerable uncertainty, which generally leads to numerous schedule disruptions. It is of interest to develop pre-schedules that can absorb disruptions in activity durations without affecting the planning of other activities, such that co-ordination of resources and material procurement for each of the activities can be performed as smoothly as possible. The objective of this paper is to develop and evaluate various approaches for constructing a stable pre-schedule, which is unlikely to undergo major changes when it needs to be repaired as a reaction to minor activity duration disruptions.

Seismic Behaviour of SMA-Reinforced Slender Concrete Shear Walls

Superelastic Shape Memory Alloys (SE-SMA) have provided a viable novel alternative to conventional steel reinforcement for the construction of earthquake-resilient structures. The capacity of SE-SMA to recover from high strains upon unloading provides the mechanism required to develop self-centering smart structures. Shear walls are routinely used seismic force resisting systems in concrete construction, which makes them qualified candidates for the application of SE-SMA longitudinal reinforcement. The integration of SE-SMA into a hybrid-reinforced flexural system is expected to rectify inelastic lateral displacements and economize the cost of post-disaster repair. A large-scale slender superelastic Nitinol-reinforced concrete shear wall was tested numerically and experimentally, along with a control specimen, under quasi-static load reversals to assess seismic performance. The results of the SE-SMA wall demonstrated efficient dissipation of seismic energy to achieve high drift recovery and easily repairable damage, suggesting a low probability of demolition and substantial savings over the lifetime of the structure

Analysis of Heat Transfer and Pressure Drop for a Gas Flowing Through a set of Multiple Parallel Flat Plates at High Temperatures

Equations were derived representing heat transfer and pressure drop for a gas flowing in the passages of a heater composed of a series of parallel flat plates. The plates generated heat which was transferred to the flowing gas by convection. The relatively high temperature level of this system necessitated the consideration of heat transfer between the plates by radiation. The equations were solved on an IBM 704 computer, and results were obtained for hydrogen as the working fluid for a series of cases with a gas inlet temperature of 200 R, an exit temperature of 5000 0 R, and exit Mach numbers ranging from 0.2 to O.8. The length of the heater composed of the plates ranged from 2 to 4 feet, and the spacing between the plates was varied from 0.003 to 0.01 foot. Most of the results were for a five- plate heater, but results are also given for nine plates to show the effect of increasing the number of plates. The heat generation was assumed to be identical for each plate but was varied along the length of the plates. The axial variation of power used to obtain the results presented is the so-called "2/3-cosine variation." The boundaries surrounding the set of plates, and parallel to it, were assumed adiabatic, so that all the power generated in the plates went into heating the gas. The results are presented in plots of maximum plate and maximum adiabatic wall temperatures as functions of parameters proportional to f(L/D), for the case of both laminar and turbulent flow. Here f is the Fanning friction factor and (L/D) is the length to equivalent diameter ratio of the passages in the heater. The pressure drop through the heater is presented as a function of these same parameters, the exit Mach number, and the pressure at the exit of the heater

Low energy digital circuits in advanced nanometer technologies

The demand for portable devices and the continuing trend towards the Internet ofThings (IoT) have made of energy consumption one of the main concerns in the industry and researchers. The most efficient way of reducing the energy consump-tion of digital circuits is decreasing the supply voltage (Vdd) since the dynamicenergy quadratically depends onVdd. Several works have shown that an optimumsupply voltage exists that minimizes the energy consumption of digital circuits. This optimum supply voltage is usually around 200 mV and 400 mV dependingon the circuit and technology used. To obtain these low supply voltages, on-chipdc-dc converters with high efficiency are needed.This thesis focuses on the study of subthreshold digital systems in advancednanometer technologies. These systems usually can be divided into a Power Man-agement Unit (PMU) and a digital circuit operating at the subthreshold regime.In particular, while considering the PMU, one of the key circuits is the dc-dcconverter. This block converts the voltage from the power source (battery, supercapacitor or wireless power transfer link) to a voltage between 200 mV and 400mV in order to power the digital circuit. In this thesis, we developed two chargerecycling techniques in order to improve the efficiency of switched capacitors dc-dcconverters. The first one is based on a technique used in adiabatic circuits calledstepwise charging. This technique was used in circuits and applications wherethe switching consumption of a big capacitance is very important. We analyzedthe possibility of using this technique in switched capacitor dc-dc converters withintegrated capacitors. We showed through measurements that a 29% reductionin the gate drive losses can be obtained with this technique. The second one isa simplification of stepwise charging which can be applied in some architecturesof switched capacitors dc-dc converters. We also fabricated and tested a dc-dcconverter with this technique and obtained a 25% energy reduction in the drivingof the switches that implement the converter.Furthermore, we studied the digital circuit working in the subthreshold regime,in particular, operating at the minimum energy point. We studied different modelsfor circuits working in these conditions and improved them by considering thedifferences between the NMOS and PMOS transistors. We obtained an optimumNMOS/PMOS leakage current imbalance that minimizes the total leakage energy per operation. This optimum depends on the architecture of the digital circuitand the input data. However, we also showed that important energy reductionscan be obtained by operating at a mean optimum imbalance. We proposed two techniques to achieve the optimum imbalance. We used aFully Depleted Silicon on Insulator (FD-SOI) 28 nm technology for most of the simulations, but we also show that these techniques can be applied in traditionalbulk CMOS technologies. The first one consists in using the back plane voltage of the transistors (or bulk voltage in traditional CMOS) to adjust independently theleakage current of the NMOS and PMOS transistor to work under the optimum NMOS/PMOS leakage current imbalance. We called this approach the OptimumBack Plane Biasing (OBB). A second technique consists of using the length of the transistors to adjust this leakage current imbalance. In the subthreshold regimeand in advanced nanometer technologies a moderate increase in the length has little impact in the output capacitance of the gates and thus in the dynamic energy.We called this approach an Asymmetric Length Biasing (ALB). Finally, we use these techniques in some basic circuits such as adders. We show that around 50% energy reduction can be obtained, in a wide range of frequency while working near the minimum energy point and using these techniques. The main contributions of this thesis are: • Analysis of the stepwise charging technique in small capacitances. •Implementation of stepwise charging technique as a charge recycling tech-nique for efficiency improvement in switched capacitor dc-dc converters. • Development of a charge sharing technique for efficiency improvement inswitched capacitor dc-dc converters. • Analysis of minimum operating voltage of digital circuits due to intrinsicnoise and the impact of technology scaling in this minimum. • Improvement in the modeling of the minimum energy point while considering NMOS and PMOS transistors difference. • Demonstration of the existence of an optimum leakage current imbalance be-tween the NMOS and PMOS transistors that minimizes energy consumptionin the subthreshold regiion. • Development of a back plane (bulk) voltage strategy for working in this optimum.• Development of a sizing strategy for working in the aforementioned optimum. • Analysis of the impact of architecture and input data on the optimum im-balance. The thesis is based on the publications [1–8]. During the Ph.D. program, other publications were generated [9–16] that are partially related with the thesis butwere not included in it.La constante demanda de dispositivos portables y los avances hacia la Internet de las Cosas han hecho del consumo de energía uno de los mayores desafíos y preocupación en la industria y la academia. La forma más eficiente de reducir el consumo de energía de los circuitos digitales es reduciendo su voltaje de alimentación ya que la energía dinámica depende de manera cuadrática con dicho voltaje. Varios trabajos demostraron que existe un voltaje de alimentación óptimo, que minimiza la energía consumida para realizar cierta operación en un circuito digital, llamado punto de mínima energía. Este óptimo voltaje se encuentra usualmente entre 200 mV y 400 mV dependiendo del circuito y de la tecnología utilizada. Para obtener estos voltajes de alimentación de la fuente de energía, se necesitan conversores dc-dc integrados con alta eficiencia. Esta tesis se concentra en el estudio de sistemas digitales trabajando en la región sub umbral diseñados en tecnologías nanométricas avanzadas (28 nm). Estos sistemas se pueden dividir usualmente en dos bloques, uno llamado bloque de manejo de potencia, y el segundo, el circuito digital operando en la region sub umbral. En particular, en lo que corresponde al bloque de manejo de potencia, el circuito más crítico es en general el conversor dc-dc. Este circuito convierte el voltaje de una batería (o super capacitor o enlace de transferencia inalámbrica de energía o unidad de cosechado de energía) en un voltaje entre 200 mV y 400 mV para alimentar el circuito digital en su voltaje óptimo. En esta tesis desarrollamos dos técnicas que, mediante el reciclado de carga, mejoran la eficiencia de los conversores dc-dc a capacitores conmutados. La primera es basada en una técnica utilizada en circuitos adiabáticos que se llama carga gradual o a pasos. Esta técnica se ha utilizado en circuitos y aplicaciones en donde el consumo por la carga y descarga de una capacidad grande es dominante. Nosotros analizamos la posibilidad de utilizar esta técnica en conversores dc-dc a capacitores conmutados con capacitores integrados. Se demostró a través de medidas que se puede reducir en un 29% el consumo debido al encendido y apagado de las llaves que implementan el conversor dc-dc. La segunda técnica, es una simplificación de la primera, la cual puede ser aplicada en ciertas arquitecturas de conversores dc-dc a capacitores conmutados. También se fabricó y midió un conversor con esta técnica y se obtuvo una reducción del 25% en la energía consumida por el manejo de las llaves del conversor. Por otro lado, estudiamos los circuitos digitales operando en la región sub umbral y en particular cerca del punto de mínima energía. Estudiamos diferentes modelos para circuitos operando en estas condiciones y los mejoramos considerando las diferencias entre los transistores NMOS y PMOS. Mediante este modelo demostramos que existe un óptimo en la relación entre las corrientes de fuga de ambos transistores que minimiza la energía de fuga consumida por operación. Este óptimo depende de la arquitectura del circuito digital y ademas de los datos de entrada del circuito. Sin embargo, demostramos que se puede reducir el consumo de manera considerable al operar en un óptimo promedio. Propusimos dos técnicas para alcanzar la relación óptima. Utilizamos una tecnología FD-SOI de 28nm para la mayoría de las simulaciones, pero también mostramos que estas técnicas pueden ser utilizadas en tecnologías bulk convencionales. La primer técnica, consiste en utilizar el voltaje de la puerta trasera (o sustrato en CMOS convencional) para ajustar de manera independiente las corrientes del NMOS y PMOS para que el circuito trabaje en el óptimo de la relación de corrientes. Esta técnica la llamamos polarización de voltaje de puerta trasera óptimo. La segunda técnica, consiste en utilizar los largos de los transistores para ajustar las corrientes de fugas de cada transistor y obtener la relación óptima. Trabajando en la región sub umbral y en tecnologías avanzadas, incrementar moderadamente el largo del transistor tiene poco impacto en la energía dinámica y es por eso que se puede utilizar. Finalmente, utilizamos estas técnicas en circuitos básicos como sumadores y mostramos que se puede obtener una reducción de la energía consumida de aproximadamente 50%, en un amplio rango de frecuencias, mientras estos circuitos trabajan cerca del punto de energía mínima. Las principales contribuciones de la tesis son: • Análisis de la técnica de carga gradual o a pasos en capacidades pequeñas. • Implementación de la técnica de carga gradual para la mejora de eficiencia de conversores dc-dc a capacitores conmutados. • Simplificación de la técnica de carga gradual para mejora de la eficiencia en algunas arquitecturas de conversores dc-dc de capacitores conmutados. • Análisis del mínimo voltaje de operación en circuitos digitales debido al ruido intrínseco del dispositivo y el impacto del escalado de las tecnologías en el mismo. • Mejoras en el modelado del punto de energía mínima de operación de un circuito digital en el cual se consideran las diferencias entre el transistor PMOS y NMOS. • Demostración de la existencia de un óptimo en la relación entre las corrientes de fuga entre el NMOS y PMOS que minimiza la energía de fugas consumida en la región sub umbral. • Desarrollo de una estrategia de polarización del voltaje de puerta trasera para que el circuito digital trabaje en el óptimo antes mencionado. • Desarrollo de una estrategia para el dimensionado de los transistores que componen las compuertas digitales que permite al circuito digital operar en el óptimo antes mencionado. • Análisis del impacto de la arquitectura del circuito y de los datos de entrada del mismo en el óptimo antes mencionado

Generating Strong Diversity of Opinions: Agent Models of Continuous Opinion Dynamics

Opinion dynamics is the study of how opinions in a group of individuals change over time. A goal of opinion dynamics modelers has long been to find a social science-based model that generates strong diversity -- smooth, stable, possibly multi-modal distributions of opinions. This research lays the foundations for and develops such a model. First, a taxonomy is developed to precisely describe agent schedules in an opinion dynamics model. The importance of scheduling is shown with applications to generalized forms of two models. Next, the meta-contrast influence field (MIF) model is defined. It is rooted in self-categorization theory and improves on the existing meta-contrast model by providing a properly scaled, continuous influence basis. Finally, the MIF-Local Repulsion (MIF-LR) model is developed and presented. This augments the MIF model with a formulation of uniqueness theory. The MIF-LR model generates strong diversity. An application of the model shows that partisan polarization can be explained by increased non-local social ties enabled by communications technology

Continuous-Time Quantum Walks: Models for Coherent Transport on Complex Networks

This paper reviews recent advances in continuous-time quantum walks (CTQW) and their application to transport in various systems. The introduction gives a brief survey of the historical background of CTQW. After a short outline of the theoretical ideas behind CTQW and of its relation to classical continuous-time random walks (CTRW) in Sec.~2, implications for the efficiency of the transport are presented in Sec.~3. The fourth section gives an overview of different types of networks on which CTQW have been studied so far. Extensions of CTQW to systems with long-range interactions and with static disorder are discussed in section V. Systems with traps, i.e., systems in which the walker's probability to remain inside the system is not conserved, are presented in section IV. Relations to similar approaches to the transport are studied in section VII. The paper closes with an outlook on possible future directions.Comment: review article to appear in Physics Reports, 39 pages, 44 figure

Reconfigurable photonic crystal

Tunability and programmability are highly demanded for silicon photonic integrated circuits (PICs) to expand their applications in the next-generation photonics. The main objective of this thesis is to develop several reconfigurable and programmable photonic crystal (PC) devices. In Chapter 2, we developed a relatively general nanofabrication process for integrating PC devices with movable mechanical components on silicon-on-insulator (SOI) wafers. We also investigated grating coupling technology, to facilitate coupling lights into and out of PC devices. In Chapter 3, we developed an all-optical programmable PC device that integrates digital micromirror device (DMD), photo-responsive LC, and PC technologies. We demonstrated the functionality and programmability of the device, by forming a point-defect cavity, a straight waveguide, and a waveguide bend on the single device. In Chapter 4, we developed two types of reconfigurable PC devices by leveraging the strengths of optical nanobeam and nano-electro-mechanical systems (NEMS) technologies. The first device consists of an array of movable nanobeams. Each nanobeam is an electrostatically tunable photonic element in a PC waveguide. We demonstrated the capability of the device to engineer different photonic bandgaps, by tuning one unit in group of two neighboring nanobeam units, tuning one or two in group of three units, and forming two reconfigurable PCs, on the single device. To achieve a higher-level integration, we also theoretically studied another reconfigurable PC integrating an array of mechanical tunable nanobeams with an array of fixed pillars into the top silicon layer of a SOI wafer. In Chapter 5, we developed two tunable photonic crystal-cantilever cavity (PC3) resonators. The first device has an NEMS cantilever embedded into a L6 cavity in a PC slab. The second device has a similar cantilever to insert into a nanobeam-base waveguide. We studied bending characteristics of the cantilever and optical characteristics of these two devices at different applied voltages. In Chapter 6, we conducted theoretical investigation on a nano-opto-mechanical reconfigurable PIC device consisting of an array of silicon plugs and a 2D PC slab. We theoretically demonstrated that a point-defect cavity, a line-defect waveguide, and a waveguide bend can be configured in the PC slab, by inserting different plugs into an air hole, a straight line of holes, and an L-shape line of holes