Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures

Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Microstructure and processing effects on stress and reliability for through-silicon vias (TSVs) in 3D integrated circuits

Copper (Cu) Through-silicon via (TSV) is a key enabling element that provides the vertical connection between stacked dies in three-dimensional (3D) integration. The thermal expansion mismatch between Cu and Si induces complex stresses in and around the TSV structures, which can degrade the performance and reliability of 3DICs and are key concerns for technology development. In this dissertation, the effects of Cu microstructure and processing conditions on the stress characteristics and reliability of the TSV structure are studied. First, the stress characteristics of Cu TSV structures are investigated using the substrate curvature method. The substrate curvature measurement was supplemented by microstructure and finite element analyses (FEA) to investigate the mechanisms for the linear and nonlinear stress-temperature behaviors observed for the TSV structure. Implications of the near surface stress on carrier mobility change and device keep-out zone (KOZ) are discussed. Second, via extrusion, an important yield and reliability issue for 3D integration, is analyzed. Synchrotron x-ray microdiffraction technique was introduced for direct measurements of local stress and material behaviors in and around the TSV. Local plasticity near the top of the via was observed which provided direct experimental evidence to support the plasticity mechanism of via extrusion. An analytical model and FEA were used to analyze via extrusion based on local plasticity. Next, the effect of Cu microstructure effect on the thermomechanical behaviors of TSVs is investigated. The contribution from grain boundary and interfacial diffusion on via extrusion and the relaxation mechanisms are discussed. Potential approaches to minimize via extrusion are proposed. Finally, the stress characteristics of 3D die stack structures are studied using synchrotron x-ray microdiffraction. High resolution stress mappings were performed and verified by finite element analysis (FEA). FEA was further developed to estimate the stress effect on device mobility changes and the warpage of the integrated structure.Materials Science and Engineerin

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

XNAP: A Novel Two-Dimensional X-Ray Detector for Time Resolved Synchrotron Applications

The XNAP project develops a demonstration system for a spatially resolving detector with timing capabilities in the nanosecond range. A dense array of avalanche photodiodes is combined with multiple readout ASICs to build the detector hybrid. On an area of nearly 1 cm2, single photons can be counted within each of the 1k pixels. After 20 years of continuous improvements during operation, the ESRF Synchrotron is going to be upgraded substantially by the replacement of major parts of the source and the beamlines. For experimental techniques that will benefit from the increased brilliance, research into X-ray detectors is required. The requirements for the novel detector are composed of the distinguished properties of multiple state-of-the-art detector systems, shifted towards technical limits. The specification is transferred into the design of the sensor, ASIC, interposing structure and the readout system. A smaller prototype detector is built to resolve implementation challenges ahead of its large-scale accomplishment. Emphasis is put on the ASIC, and parallel approaches for the interconnecting technology and the readout system are carried out. The usability of the smaller prototype system is demonstrated with measurements of microfocus X-ray and Synchrotron light. Parts of the final detector are characterized at the laboratory prior to its commissioning

Compliant Chip-to-Package Interconnects for Wafer Level Packaging

Ph.DDOCTOR OF PHILOSOPH

High Efficiency Polymer based Direct Multi-jet Impingement Cooling Solution for High Power Devices

Liquid jet impingement cooling is an efficient cooling technique where the liquid coolant is directly ejected from nozzles on the chip backside resulting in a high cooling efficiency due to the absence of the TIM and the lateral temperature gradient. In literature, several Si-fabrication based impingement coolers with nozzle diameters of a few distributed returns or combination of micro-channels and impingement nozzles. The drawback of this Si processing of the cooler is the high fabrication cost. Other fabrication methods for nozzle diameters for ceramic and metal. Low cost fabrication methods, including injection molding and 3D printing have been introduced for much larger nozzle diameters (mm range) with larger cooler dimensions. These dimensions and processes are however not compatible with the chip packaging process flow. This PhD focuses on the modeling, design, fabrication and characterization of a micro-scale liquid impingement cooler using advanced, yet cost efficient, fabrication techniques. The main objectives are: (a) development of a modeling methodology to optimize the cooler geometry; (b) exploring low cost fabrication methods for the package level impingement jet cooler; (c) experimental thermal and hydraulic characterization and analysis of the fabricated coolers; (d) applying the direct impingement jet cooling solutions to different applications

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications