Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability.
Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface
Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well.
Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic
