Integrated Microwave Photonic Processors using Waveguide Mesh Cores

Integrated microwave photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint and cost. Application Specific Photonic Integrated Circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long-development times and costly implementations. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable Microwave Photonic processor, where a common hardware implemented by the combination of microwave, photonic and electronic subsystems, realizes different functionalities through programming. Here, we propose the first-ever generic-purpose Microwave Photonic processor concept and architecture. This versatile processor requires a powerful end-to-end field-based analytical model to optimally configure all their subsystems as well as to evaluate their performance in terms of the radiofrequency gain, noise and dynamic range. Therefore, we develop a generic model for integrated Microwave Photonics systems. The key element of the processor is the reconfigurable optical core. It requires high flexibility and versatility to enable reconfigurable interconnections between subsystems as well as the synthesis of photonic integrated circuits. For this element, we focus on a 2-dimensional photonic waveguide mesh based on the interconnection of tunable couplers. Within the framework of this Thesis, we have proposed two novel interconnection schemes, aiming for a mesh design with a high level of versatility. Focusing on the hexagonal waveguide mesh, we explore the synthesis of a high variety of photonic integrated circuits and particular Microwave Photonics applications that can potentially be performed on a single hardware. In addition, we report the first-ever demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate a world-record number of functionalities on a single photonic integrated circuit enabling over 30 different functionalities from the 100 that could be potentially obtained with a simple seven hexagonal cell structure. The resulting device can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks as well as quantum information systems. Our work is an important step towards this paradigm and sets the base for a new era of generic-purpose photonic integrated systems.Los dispositivos integrados de fotónica de microondas ofrecen soluciones optimizadas para los sistemas de información y comunicación. Generalmente, están compuestos por diferentes arquitecturas en las que subsistemas ópticos y electrónicos se integran para optimizar las prestaciones, el consumo, el tamaño y el coste del dispositivo final. Hasta ahora, los circuitos/chips de propósito específico se han diseñado para proporcionar una funcionalidad concreta, requiriendo así un número considerable de iteraciones entre las etapas de diseño, fabricación y medida, que origina tiempos de desarrollo largos y costes demasiado elevados. Una alternativa, inspirada por las FPGA (del inglés Field Programmable Gate Array), es el procesador fotónico programable. Este dispositivo combina la integración de subsistemas de microondas, ópticos y electrónicos para realizar, mediante la programación de los mismos y sus interconexiones, diferentes funcionalidades. En este trabajo, proponemos por primera vez el concepto del procesador de propósito general, así como su arquitectura. Además, con el fin de diseñar, optimizar y evaluar las prestaciones básicas del dispositivo, hemos desarrollado un modelo analítico extremo a extremo basado en las componentes del campo electromagnético. El modelo desarrollado proporciona como resultado la ganancia, el ruido y el rango dinámico global para distintas configuraciones de modulación y detección, en función de los subsistemas y su configuración. El elemento principal del procesador es su núcleo óptico reconfigurable. Éste requiere un alto grado de flexibilidad y versatilidad para reconfigurar las interconexiones entre los distintos subsistemas y para sintetizar los circuitos para el procesado óptico. Para este subsistema, proponemos el diseño de guías de onda reconfigurables para la creación de mallados bidimensionales. En el marco de esta tesis, hemos propuesto dos nuevos nodos de interconexión óptica para mallas reconfigurables, con el objetivo de obtener un mayor grado de versatilidad. Una vez escogida la malla hexagonal para el núcleo del procesador, hemos analizado la configuración de un gran número de circuitos fotónicos integrados y de funcionalidades de fotónica de microondas. El trabajo se ha completado con la demonstración de la primera malla reconfigurable integrada en un chip de silicio, demostrando además la síntesis de 30 de las 100 funcionalidades que potencialmente se pueden obtener con la malla diseñada compuesta de 7 celdas hexagonales. Este hecho supone un record frente a los sistemas de propósito específico. El sistema puede aplicarse en diferentes campos como las comunicaciones, los sensores químicos y biomédicos, el procesado de señales, la gestión y procesamiento de redes y los sistemas de información cuánticos. El conjunto del trabajo realizado representa un paso importante en la evolución de este paradigma, y sienta las bases para una nueva era de dispositivos fotónicos de propósito general.Els dispositius integrats de Fotònica de Microones oferixen solucions optimitzades per als sistemes d'informació i comunicació. Generalment, estan compostos per diferents arquitectures en què subsistemes òptics i electrònics s'integren per a optimitzar les prestacions, el consum, la grandària i el cost del dispositiu final. Fins ara, els circuits/xips de propòsit específic s'han dissenyat per a proporcionar una funcionalitat concreta, requerint així un nombre considerable d'iteracions entre les etapes de disseny, fabricació i mesura, que origina temps de desenrotllament llargs i costos massa elevats. Una alternativa, inspirada per les FPGA (de l'anglés Field Programmable Gate Array), és el processador fotònic programable. Este dispositiu combina la integració de subsistemes de microones, òptics i electrònics per a realitzar, per mitjà de la programació dels mateixos i les seues interconnexions, diferents funcionalitats. En este treball proposem per primera vegada el concepte del processador de propòsit general, així com la seua arquitectura. A més, a fi de dissenyar, optimitzar i avaluar les prestacions bàsiques del dispositiu, hem desenrotllat un model analític extrem a extrem basat en els components del camp electromagnètic. El model desenrotllat proporciona com resultat el guany, el soroll i el rang dinàmic global per a distintes configuracions de modulació i detecció, en funció dels subsistemes i la seua configuració. L'element principal del processador és el seu nucli òptic reconfigurable. Este requerix un alt grau de flexibilitat i versatilitat per a reconfigurar les interconnexions entre els distints subsistemes i per a sintetitzar els circuits per al processat òptic. Per a este subsistema, proposem el disseny de guies d'onda reconfigurables per a la creació de mallats bidimensionals. En el marc d'esta tesi, hem proposat dos nous nodes d'interconnexió òptica per a malles reconfigurables, amb l'objectiu d'obtindre un major grau de versatilitat. Una vegada triada la malla hexagonal per al nucli del processador, hem analitzat la configuració d'un gran nombre de circuits fotónicos integrats i de funcionalitats de fotónica de microones. El treball s'ha completat amb la demostració de la primera malla reconfigurable integrada en un xip de silici, demostrant a més la síntesi de 30 de les 100 funcionalitats que potencialment es poden obtindre amb la malla dissenyada composta de 7 cèl·lules hexagonals. Este fet suposa un rècord enfront dels sistemes de propòsit específic. El sistema pot aplicarse en diferents camps com les comunicacions, els sensors químics i biomèdics, el processat de senyals, la gestió i processament de xarxes i els sistemes d'informació quàntics. El conjunt del treball realitzat representa un pas important en l'evolució d'este paradigma, i assenta les bases per a una nova era de dispositius fotónicos de propòsit general.Pérez López, D. (2017). Integrated Microwave Photonic Processors using Waveguide Mesh Cores [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/91232TESI

Parallel and Distributed Computing

The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing

Multipurpose silicon photonics signal processor core

[EN] Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.J.C. acknowledges funding from the ERC Advanced Grant ERC-ADG-2016-741415 UMWP-Chip, I.G. acknowledges the funding through the Spanish MINECO Ramon y Cajal program. D.P. acknowledges financial support from the UPV through the FPI predoctoral funding scheme. D.J.T. acknowledges funding from the Royal Society for his University Research Fellowship.Pérez-López, D.; Gasulla Mestre, I.; Crudgington, L.; Thomson, DJ.; Khokhar, AZ.; Li, K.; Cao, W.... (2017). Multipurpose silicon photonics signal processor core. Nature Communications. 8(1925):1-9. https://doi.org/10.1038/s41467-017-00714-1S1981925Doerr, C. R. & Okamoto, K. Advances in silica planar lightwave circuits. J. Lightw. Technol. 24, 4763–4789 (2006).Coldren, L. A. et al. High performance InP-based photonic ICs—A tutorial. J. Lightw. Technol 29, 554–570 (2011).Soref, R. The past, present, and future of silicon photonics. IEEE J. Sel. Top. Quantum Electron. 12, 1678–1687 (2006).Bogaerts, W. Design challenges in silicon photonics. IEEE J. Sel. Top. Quantum Electron. 20, 8202008 (2014).Bogaerts, W. et al. Nanophotonic waveguides in silicon-on-insulator fabricated with CMOS technology. J. Lightw. Technol. 23, 401–412 (2005).Smit, M. K. et al. An introduction to InP-based generic integration technology. Semicond. Sci. Technol. 29, 083001 (2014).Leinse, A. et al. TriPleX waveguide platform: low-loss technology over a wide wavelength range. Proc. SPIE 8767, 87670E (2013).Kish, F. et al. From visible light-emitting diodes to large-scale III–V photonic integrated circuits. Proc. IEEE 101, 2255–2270 (2013).Heck, M. J. R. et al. Hybrid silicon photonic integrated circuit technology. IEEE J. Sel. Top. Quantum Electron. 19, 6100117 (2013).Sacher, W. et al. Multilayer silicon nitride-on-silicon integrated photonic platforms and devices. J. Lightw. Technol. 33, 901–910 (2015).Asghari, M. Silicon photonics: A low cost integration platform for datacom and telecom applications. In OFC/NFOEC 2008 – 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference 1–10 (San Diego, USA, 2008).Melati, D. et al. Integrated all-optical MIMO demultiplexer for mode- and wavelength-division-multiplexed transmission. Opt. Lett. 42, 342–345 (2017).Waterhouse, R. & Novak, D. Realizing 5G: microwave photonics for 5G mobile wireless systems. IEEE Microw. Mag. 16, 84–92 (2015).Marpaung, D. et al. Integrated microwave photonics. Laser Photon. Rev. 7, 506–538 (2013).Iezekiel, S., Burla, M., Klamkin, J., Marpaung, D. & Capmany, J. RF engineering meets optoelectronics: Progress in integrated microwave photonics. IEEE Microw. Mag. 16, 28–45 (2015).Technology focus on microwave photonics. Nat. Photon. 5, 723 (2011).Ghelfi, P. et al. A fully photonics-based coherent radar system. Nature 507, 341–345 (2014).Heideman, R. G. TriPleX™-based integrated optical ring resonators for lab-ona-chip-and environmental detection. IEEE J. Sel. Top. Quantum Electron. 18, 1583–1596 (2012).Estevez, M. C., Alvarez, M. & Lechuga, L. Integrated optical devices for lab-on-a-chip biosensing applications. Laser Photon. Rev. 6, 463–487 (2012).Almeida, V. R., Barrios, C. A., Panepucci, R. & Lipson, M. All-optical control of light on a silicon chip. Nature 431, 1081–1084 (2004).Norberg, E. J., Guzzon, R. S., Parker, J. S., Johansson, L. A. & Coldren, L. A. Programmable photonic microwave filters monolithically integrated in InP/InGaAsP. J. Lightw. Technol. 29, 1611–1619 (2011).Wang, J. et al. Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip. Nat. Commun. 6, 5957 (2015).Hill, M. T. et al. A fast low power optical memory based on coupled micro-ring lasers. Nature 432, 206–209 (2004).Slavík, R. et al. Photonic temporal integrator for all-optical computing. Opt. Express 16, 18202–18214 (2008).Sun, C. et al. A monolithically-integrated chip-to-chip optical link in bulk CMOS. IEEE J. Solid-State Circ. 50, 828–844 (2015).Sun, C. et al. Single-chip microprocessor that communicates directly using light. Nature 528, 534–538 (2015).Assefa, S. et al. in Optical Fibre Communication Conference OMM6, https://www.osapublishing.org/abstract.cfm?uri=OFC-2011-OMM6 (Optical Society of America, 2011).Peruzzo, A. et al. Multimode quantum interference of photons in multiport integrated devices. Nat. Commun. 2, 224 (2011).Bonneau, D. et al. Quantum interference and manipulation of entanglement in silicon wire waveguide quantum circuits. N. J. Phys. 14, 045003 (2012).Metcalf, B. J. et al. Multiphoton quantum interference in a multiport integrated photonic device. Nat. Commun. 4, 1356 (2013).Muñoz, P. et al. in 16th International Conference on Transparent Optical Networks (ICTON), 1–4 (Graz, 2014).Ribeiro, A. et al. Demonstration of a 4×4-port universal linear circuit. Optica 3, 1348–1357 (2016).Liu, W. et al. A fully reconfigurable photonic integrated signal processor. Nat. Photon 10, 190–195 (2016).Graydon, O. Birth of the programmable optical chip. Nat. Photon 10, 1 (2016).Pérez, D., Gasulla, I. & Capmany, J. Software-defined reconfigurable microwave photonics processor. Opt. Express 23, 14640–14654 (2015).Miller, D. A. B. Self-configuring universal linear optical component. Photon. Res. 1, 1–15 (2013).Miller, D. A. B. Self-aligning universal beam coupler. Opt. Express 21, 6360–6370 (2013).Clements, W. R. et al. Optimal design for universal multiport interferometers. Optica 3, 1460–1465 (2016).Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J. & Lowery, A. J. Programmable photonic signal processor chip for radiofrequency applications. Optica 2, 854–859 (2015).Capmany, J., Gasulla, I. & Pérez, D. Microwave photonics: The programmable processor. Nat. Photon. 10, 6–8 (2016).Pérez, D., Gasulla., Capmany, J. & Soref, R. A. Reconfigurable lattice mesh designs for programmable photonic processors. Opt. Express 24, 12093–12106 (2016).Madsen, C. K. & Zhao, J. H. Optical Filter Design and Analysis: A Signal Processing Approach. 1st edn. (Wiley, 1999).Jinguji, K. Synthesis of coherent two-port lattice-form optical delay-line circuit. J. Lightw. Technol. 13, 73–82 (1995).Jinguji, K. Synthesis of coherent two-port Optical delay-line circuit with ring waveguides. J. Lightw. Technol. 14, 1882–1898 (1996).Madsen, C. K. General IIR optical filter design for WDM applications using all-pass filters. J. Lightw. Technol. 18, 860–868 (2000).Burla, M. et al. On-chip CMOS compatible reconfigurable optical delay line with separate carrier tuning for microwave photonic signal processing. Opt. Express 19, 21475–21484 (2011).Yariv, A. et al. Coupled resonator optical waveguides: a proposal and analysis. Opt. Lett. 24, 711–713 (1999).Hebner, J. E. et al. Distributed and localized feedback in microresonator sequences for linear and nonlinear optics. J. Opt. Soc. Am. B. 21, 1665–1673 (2004).Fandiño, J. S. et al. A monolithic integrated photonic microwave filter. Nat. Photon. 11, 124–129 (2017).Miller, D. A. B. All linear optical devices are mode converters. Opt. Express 20, 23985–23993 (2012).Reck, M. et al. Experimental realization of any discrete unitary operator. Phys. Rev. Lett. 73, 58–61 (1994).Carolan, J. et al. Universal linear optics. Science 349, 711 (2015).Nielsen, M. A. & Chuang, I. L. Quantum Computation and Quantum Information. 1st edn. (Cambridge University Press, 2001).Miller, D. A. B. Perfect optics with imperfect components. Optica 2, 747–750 (2015).Grillanda, S. et al. Non-invasive monitoring and control in silicon photonics using CMOS integrated electronics. Optica 1, 129–136 (2014)

Auto-routing algorithm for field-programmable photonic gate arrays

[EN] Programmable multipurpose photonic integrated circuits require software routines to make use of their flexible operation as desired. In this work, we propose and demonstrate the use of a modified tree-search algorithm to automatically determine the optimum optical path in a field-programmable photonic gate array (FPPGA), based on end-user specifications, circuit architecture and imperfections in the realized FPPGA arising, for example, from fabrication variations. In such a scenario, the proposed algorithm only requires the hardware topology and the location of the connections of the FPPGA defining the optical path to be programmed. The routine is able to optimize the path over multiple and competing objectives like the overall length, accumulated loss and power consumption. In addition, should any region of the circuit suffer from any potential damage that may affect the device performance, this algorithm is also able to provide basic self-healing and fault-tolerance capabilities by supplying alternative paths through the photonic arrangement.The authors acknowledge financial support by the ERC ADG-2016 UMWP-Chip ERC-2016- ADG-741415, the ERC PoC-2019 FPPAs ERC-2019-POC-859927, the Generalitat Valenciana Future MWP technologies and applications PROMETEO 2017/103 research excellency award, and the COST Action CA16220 EUIMWP, the Advanced Instrumentation for World Class Microwave Photonics Research IDIFEDER/2018/031 and the Infraestructura para caracterizacion de Chips Fotonicos EQC2018-004683-PLópez-Hernández, A.; Pérez-López, D.; Dasmahapatra, P.; Capmany Francoy, J. (2020). Auto-routing algorithm for field-programmable photonic gate arrays. Optics Express. 28(1):737-752. https://doi.org/10.1364/oe.382753737752281Soref, R. (2006). The Past, Present, and Future of Silicon Photonics. IEEE Journal of Selected Topics in Quantum Electronics, 12(6), 1678-1687. doi:10.1109/jstqe.2006.883151Streshinsky, M., Ding, R., Liu, Y., Novack, A., Galland, C., Lim, A. E.-J., … Hochberg, M. (2013). The Road to Affordable, Large-Scale Silicon Photonics. Optics and Photonics News, 24(9), 32. doi:10.1364/opn.24.9.000032Smit, M., Leijtens, X., Ambrosius, H., Bente, E., van der Tol, J., Smalbrugge, B., … van Veldhoven, R. (2014). An introduction to InP-based generic integration technology. Semiconductor Science and Technology, 29(8), 083001. doi:10.1088/0268-1242/29/8/083001Carroll, L., Lee, J.-S., Scarcella, C., Gradkowski, K., Duperron, M., Lu, H., … O’Brien, P. (2016). Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices. Applied Sciences, 6(12), 426. doi:10.3390/app6120426Pérez, D., Gasulla, I., & Capmany, J. (2018). Field-programmable photonic arrays. Optics Express, 26(21), 27265. doi:10.1364/oe.26.027265Pérez, D., Gasulla, I., Capmany, J., & Soref, R. A. (2016). Reconfigurable lattice mesh designs for programmable photonic processors. Optics Express, 24(11), 12093. doi:10.1364/oe.24.012093Zhuang, L., Roeloffzen, C. G. H., Hoekman, M., Boller, K.-J., & Lowery, A. J. (2015). Programmable photonic signal processor chip for radiofrequency applications. Optica, 2(10), 854. doi:10.1364/optica.2.000854Pérez, D., Gasulla, I., Crudgington, L., Thomson, D. J., Khokhar, A. Z., Li, K., … Capmany, J. (2017). Multipurpose silicon photonics signal processor core. Nature Communications, 8(1). doi:10.1038/s41467-017-00714-1Pérez, D., & Capmany, J. (2019). Scalable analysis for arbitrary photonic integrated waveguide meshes. Optica, 6(1), 19. doi:10.1364/optica.6.000019Dijkstra, E. W. (1959). A note on two problems in connexion with graphs. Numerische Mathematik, 1(1), 269-271. doi:10.1007/bf01386390McQuillan, J., Richer, I., & Rosen, E. (1980). The New Routing Algorithm for the ARPANET. IEEE Transactions on Communications, 28(5), 711-719. doi:10.1109/tcom.1980.109472

Simulations and Algorithms on Reconfigurable Meshes With Pipelined Optical Buses.

Recently, many models using reconfigurable optically pipelined buses have been proposed in the literature. A system with an optically pipelined bus uses optical waveguides, with unidirectional propagation and predictable delays, instead of electrical buses to transfer information among processors. These two properties enable synchronized concurrent access to an optical bus in a pipelined fashion. Combined with the abilities of the bus structure to broadcast and multicast, this architecture suits many communication-intensive applications. We establish the equivalence of three such one-dimensional optical models, namely the LARPBS, LPB, and POB. This implies an automatic translation of algorithms (without loss of speed or efficiency) among these models. In particular, since the LPB is the same as an LARPBS without the ability to segment its buses, their equivalence establishes reconfigurable delays (rather than segmenting ability) as the key to the power of optically pipelined models. We also present simulations for a number of two-dimensional optical models and establish that they possess the same complexity, so that any of these models can simulate a step of one of the other models in constant time with a polynomial increase in size. Specifically, we determine the complexity of three two-dimensional optical models (the PR-Mesh, APPBS, and AROB) to be the same as the well known LR-Mesh and the cycle-free LR-Mesh. We develop algorithms for the LARPBS and PR-Mesh that are more efficient than existing algorithms in part by exploiting the pipelining, segmenting, and multicasting characteristics of these models. We also consider the implications of certain physical constraints placed on the system by restricting the distance over which two processors are able to communicate. All algorithms developed for these models assume that a healthy system is available. We present some fundamental algorithms that are able to tolerate up to N/2 faults on an N-processor LARPBS. We then extend these results to apply to other algorithms in the areas of image processing and matrix operations

An integrated associative processing system

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 97-105).by Frederick Paul Herrmann.Ph.D

Cross-Layer Rapid Prototyping and Synthesis of Application-Specific and Reconfigurable Many-accelerator Platforms

Technological advances of recent years laid the foundation consolidation of informatisationof society, impacting on economic, political, cultural and socialdimensions. At the peak of this realization, today, more and more everydaydevices are connected to the web, giving the term ”Internet of Things”. The futureholds the full connection and interaction of IT and communications systemsto the natural world, delimiting the transition to natural cyber systems and offeringmeta-services in the physical world, such as personalized medical care, autonomoustransportation, smart energy cities etc. . Outlining the necessities of this dynamicallyevolving market, computer engineers are required to implement computingplatforms that incorporate both increased systemic complexity and also cover awide range of meta-characteristics, such as the cost and design time, reliabilityand reuse, which are prescribed by a conflicting set of functional, technical andconstruction constraints. This thesis aims to address these design challenges bydeveloping methodologies and hardware/software co-design tools that enable therapid implementation and efficient synthesis of architectural solutions, which specifyoperating meta-features required by the modern market. Specifically, this thesispresents a) methodologies to accelerate the design flow for both reconfigurableand application-specific architectures, b) coarse-grain heterogeneous architecturaltemplates for processing and communication acceleration and c) efficient multiobjectivesynthesis techniques both at high abstraction level of programming andphysical silicon level.Regarding to the acceleration of the design flow, the proposed methodologyemploys virtual platforms in order to hide architectural details and drastically reducesimulation time. An extension of this framework introduces the systemicco-simulation using reconfigurable acceleration platforms as co-emulation intermediateplatforms. Thus, the development cycle of a hardware/software productis accelerated by moving from a vertical serial flow to a circular interactive loop.Moreover the simulation capabilities are enriched with efficient detection and correctiontechniques of design errors, as well as control methods of performancemetrics of the system according to the desired specifications, during all phasesof the system development. In orthogonal correlation with the aforementionedmethodological framework, a new architectural template is proposed, aiming atbridging the gap between design complexity and technological productivity usingspecialized hardware accelerators in heterogeneous systems-on-chip and networkon-chip platforms. It is presented a novel co-design methodology for the hardwareaccelerators and their respective programming software, including the tasks allocationto the available resources of the system/network. The introduced frameworkprovides implementation techniques for the accelerators, using either conventionalprogramming flows with hardware description language or abstract programmingmodel flows, using techniques from high-level synthesis. In any case, it is providedthe option of systemic measures optimization, such as the processing speed,the throughput, the reliability, the power consumption and the design silicon area.Finally, on addressing the increased complexity in design tools of reconfigurablesystems, there are proposed novel multi-objective optimization evolutionary algo-rithms which exploit the modern multicore processors and the coarse-grain natureof multithreaded programming environments (e.g. OpenMP) in order to reduce theplacement time, while by simultaneously grouping the applications based on theirintrinsic characteristics, the effectively explore the design space effectively.The efficiency of the proposed architectural templates, design tools and methodologyflows is evaluated in relation to the existing edge solutions with applicationsfrom typical computing domains, such as digital signal processing, multimedia andarithmetic complexity, as well as from systemic heterogeneous environments, suchas a computer vision system for autonomous robotic space navigation and manyacceleratorsystems for HPC and workstations/datacenters. The results strengthenthe belief of the author, that this thesis provides competitive expertise to addresscomplex modern - and projected future - design challenges.Οι τεχνολογικές εξελίξεις των τελευταίων ετών έθεσαν τα θεμέλια εδραίωσης της πληροφοριοποίησης της κοινωνίας, επιδρώντας σε οικονομικές,πολιτικές, πολιτιστικές και κοινωνικές διαστάσεις. Στο απόγειο αυτής τη ςπραγμάτωσης, σήμερα, ολοένα και περισσότερες καθημερινές συσκευές συνδέονται στο παγκόσμιο ιστό, αποδίδοντας τον όρο «Ίντερνετ των πραγμάτων».Το μέλλον επιφυλάσσει την πλήρη σύνδεση και αλληλεπίδραση των συστημάτων πληροφορικής και επικοινωνιών με τον φυσικό κόσμο, οριοθετώντας τη μετάβαση στα συστήματα φυσικού κυβερνοχώρου και προσφέροντας μεταυπηρεσίες στον φυσικό κόσμο όπως προσωποποιημένη ιατρική περίθαλψη, αυτόνομες μετακινήσεις, έξυπνες ενεργειακά πόλεις κ.α. . Σκιαγραφώντας τις ανάγκες αυτής της δυναμικά εξελισσόμενης αγοράς, οι μηχανικοί υπολογιστών καλούνται να υλοποιήσουν υπολογιστικές πλατφόρμες που αφενός ενσωματώνουν αυξημένη συστημική πολυπλοκότητα και αφετέρου καλύπτουν ένα ευρύ φάσμα μεταχαρακτηριστικών, όπως λ.χ. το κόστος σχεδιασμού, ο χρόνος σχεδιασμού, η αξιοπιστία και η επαναχρησιμοποίηση, τα οποία προδιαγράφονται από ένα αντικρουόμενο σύνολο λειτουργικών, τεχνολογικών και κατασκευαστικών περιορισμών. Η παρούσα διατριβή στοχεύει στην αντιμετώπιση των παραπάνω σχεδιαστικών προκλήσεων, μέσω της ανάπτυξης μεθοδολογιών και εργαλείων συνσχεδίασης υλικού/λογισμικού που επιτρέπουν την ταχεία υλοποίηση καθώς και την αποδοτική σύνθεση αρχιτεκτονικών λύσεων, οι οποίες προδιαγράφουν τα μετα-χαρακτηριστικά λειτουργίας που απαιτεί η σύγχρονη αγορά. Συγκεκριμένα, στα πλαίσια αυτής της διατριβής, παρουσιάζονται α) μεθοδολογίες επιτάχυνσης της ροής σχεδιασμού τόσο για επαναδιαμορφούμενες όσο και για εξειδικευμένες αρχιτεκτονικές, β) ετερογενή αδρομερή αρχιτεκτονικά πρότυπα επιτάχυνσης επεξεργασίας και επικοινωνίας και γ) αποδοτικές τεχνικές πολυκριτηριακής σύνθεσης τόσο σε υψηλό αφαιρετικό επίπεδο προγραμματισμού,όσο και σε φυσικό επίπεδο πυριτίου.Αναφορικά προς την επιτάχυνση της ροής σχεδιασμού, προτείνεται μια μεθοδολογία που χρησιμοποιεί εικονικές πλατφόρμες, οι οποίες αφαιρώντας τις αρχιτεκτονικές λεπτομέρειες καταφέρνουν να μειώσουν σημαντικά το χρόνο εξομοίωσης. Παράλληλα, εισηγείται η συστημική συν-εξομοίωση με τη χρήση επαναδιαμορφούμενων πλατφορμών, ως μέσων επιτάχυνσης. Με αυτόν τον τρόπο, ο κύκλος ανάπτυξης ενός προϊόντος υλικού, μετατεθειμένος από την κάθετη σειριακή ροή σε έναν κυκλικό αλληλεπιδραστικό βρόγχο, καθίσταται ταχύτερος, ενώ οι δυνατότητες προσομοίωσης εμπλουτίζονται με αποδοτικότερες μεθόδους εντοπισμού και διόρθωσης σχεδιαστικών σφαλμάτων, καθώς και μεθόδους ελέγχου των μετρικών απόδοσης του συστήματος σε σχέση με τις επιθυμητές προδιαγραφές, σε όλες τις φάσεις ανάπτυξης του συστήματος. Σε ορθογώνια συνάφεια με το προαναφερθέν μεθοδολογικό πλαίσιο, προτείνονται νέα αρχιτεκτονικά πρότυπα που στοχεύουν στη γεφύρωση του χάσματος μεταξύ της σχεδιαστικής πολυπλοκότητας και της τεχνολογικής παραγωγικότητας, με τη χρήση συστημάτων εξειδικευμένων επιταχυντών υλικού σε ετερογενή συστήματα-σε-ψηφίδα καθώς και δίκτυα-σε-ψηφίδα. Παρουσιάζεται κατάλληλη μεθοδολογία συν-σχεδίασης των επιταχυντών υλικού και του λογισμικού προκειμένου να αποφασισθεί η κατανομή των εργασιών στους διαθέσιμους πόρους του συστήματος/δικτύου. Το μεθοδολογικό πλαίσιο προβλέπει την υλοποίηση των επιταχυντών είτε με συμβατικές μεθόδους προγραμματισμού σε γλώσσα περιγραφής υλικού είτε με αφαιρετικό προγραμματιστικό μοντέλο με τη χρήση τεχνικών υψηλού επιπέδου σύνθεσης. Σε κάθε περίπτωση, δίδεται η δυνατότητα στο σχεδιαστή για βελτιστοποίηση συστημικών μετρικών, όπως η ταχύτητα επεξεργασίας, η ρυθμαπόδοση, η αξιοπιστία, η κατανάλωση ενέργειας και η επιφάνεια πυριτίου του σχεδιασμού. Τέλος, προκειμένου να αντιμετωπισθεί η αυξημένη πολυπλοκότητα στα σχεδιαστικά εργαλεία επαναδιαμορφούμενων συστημάτων, προτείνονται νέοι εξελικτικοί αλγόριθμοι πολυκριτηριακής βελτιστοποίησης, οι οποίοι εκμεταλλευόμενοι τους σύγχρονους πολυπύρηνους επεξεργαστές και την αδρομερή φύση των πολυνηματικών περιβαλλόντων προγραμματισμού (π.χ. OpenMP), μειώνουν το χρόνο επίλυσης του προβλήματος της τοποθέτησης των λογικών πόρων σε φυσικούς,ενώ ταυτόχρονα, ομαδοποιώντας τις εφαρμογές βάση των εγγενών χαρακτηριστικών τους, διερευνούν αποτελεσματικότερα το χώρο σχεδίασης.Η αποδοτικότητά των προτεινόμενων αρχιτεκτονικών προτύπων και μεθοδολογιών επαληθεύτηκε σε σχέση με τις υφιστάμενες λύσεις αιχμής τόσο σε αυτοτελής εφαρμογές, όπως η ψηφιακή επεξεργασία σήματος, τα πολυμέσα και τα προβλήματα αριθμητικής πολυπλοκότητας, καθώς και σε συστημικά ετερογενή περιβάλλοντα, όπως ένα σύστημα όρασης υπολογιστών για αυτόνομα διαστημικά ρομποτικά οχήματα και ένα σύστημα πολλαπλών επιταχυντών υλικού για σταθμούς εργασίας και κέντρα δεδομένων, στοχεύοντας εφαρμογές υψηλής υπολογιστικής απόδοσης (HPC). Τα αποτελέσματα ενισχύουν την πεποίθηση του γράφοντα, ότι η παρούσα διατριβή παρέχει ανταγωνιστική τεχνογνωσία για την αντιμετώπιση των πολύπλοκων σύγχρονων και προβλεπόμενα μελλοντικών σχεδιαστικών προκλήσεων

Standard quantification and measurement of damages through features characterization of surface imperfections on 3D models: an application on Architectural Heritages

Abstract Reverse Engineering techniques lead to easily obtain, even in case of wide and complex objects, high-resolution 3D models, suitably adoptable in the field of surface analysis and characterization. This research aims to propose innovative quantification and measuring approaches to diagnose and monitor damages affecting artefacts of different nature, from manufacturing to architectural heritage, performing non-destructive analyses with advanced surface metrology instruments and the potential integrations of the existing sectorial standards. General condition assessment is proposed to recognize and classify characterized pathologies by meaningful features in the form of surface imperfections, through the analysis of acquired point clouds. The method is applied to decay phenomena of an architectural artefact

Implementation and Evaluation of an NoC Architecture for FPGAs

The Networks-on-Chip (NoC) approach for designing Systems-on-Chip (SoC) is currently emerging as an advanced concept for overcoming the scalability and efficiency problems of traditional bus-based systems. A great deal of theoretical research has been done in this area that provides good insight and shows promising results. There is a great need for research in hardware implementation of NoC-based systems to determine the feasibility of implementing various topologies and protocols, and also to accurately determine what design tradeoffs are involved in NoC implementation. This thesis addresses the challenges of implementing an NoC-based system on FPGAs for running real benchmark applications. The NoC used a mesh topology and circuit-switched communication protocol. An experimental framework was developed that allowed implementation of NoC-based system from a high level specification, using the Celoxica Handel-C hardware description language. Two test applications: charged couple device (CCD) and JPEG were developed in Handel-C to be used as our benchmark applications. Both benchmarks are computational expensive and require large quantities of data transfer that will test the NoC system. Implementation results show that the NoC-based system gives superior area utilization and speed performance compared to the bus-based system, running the same benchmarks