Robust low-power digital circuit design in nano-CMOS technologies

Device scaling has resulted in large scale integrated, high performance, low-power, and low cost systems. However the move towards sub-100 nm technology nodes has increased variability in device characteristics due to large process variations. Variability has severe implications on digital circuit design by causing timing uncertainties in combinational circuits, degrading yield and reliability of memory elements, and increasing power density due to slow scaling of supply voltage. Conventional design methods add large pessimistic safety margins to mitigate increased variability, however, they incur large power and performance loss as the combination of worst cases occurs very rarely. In-situ monitoring of timing failures provides an opportunity to dynamically tune safety margins in proportion to on-chip variability that can significantly minimize power and performance losses. We demonstrated by simulations two delay sensor designs to detect timing failures in advance that can be coupled with different compensation techniques such as voltage scaling, body biasing, or frequency scaling to avoid actual timing failures. Our simulation results using 45 nm and 32 nm technology BSIM4 models indicate significant reduction in total power consumption under temperature and statistical variations. Future work involves using dual sensing to avoid useless voltage scaling that incurs a speed loss. SRAM cache is the first victim of increased process variations that requires handcrafted design to meet area, power, and performance requirements. We have proposed novel 6 transistors (6T), 7 transistors (7T), and 8 transistors (8T)-SRAM cells that enable variability tolerant and low-power SRAM cache designs. Increased sense-amplifier offset voltage due to device mismatch arising from high variability increases delay and power consumption of SRAM design. We have proposed two novel design techniques to reduce offset voltage dependent delays providing a high speed low-power SRAM design. Increasing leakage currents in nano-CMOS technologies pose a major challenge to a low-power reliable design. We have investigated novel segmented supply voltage architecture to reduce leakage power of the SRAM caches since they occupy bulk of the total chip area and power. Future work involves developing leakage reduction methods for the combination logic designs including SRAM peripherals

Analysis, quantification, and mitigation of electrical variability due to layout dependent effects in SOC designs

Variability in performance and power of 40nm and 28nm CMOS cells is highly dependent on the context in which the cells are used. In this study, the effects of context on a number of clock tree cells from standard cell libraries have been investigated. The study also demonstrated how the Litho Electrical Analyzer (LEA) tool from Cadence is used to analyze the context-dependent variability. During the study, it was observed that the device characteristics including Vth, Idsat, and Ioff are significantly affected by Layout Dependent Effects (LDE), resulting in variability of performance and power of standard cells. Moreover, the dummy diffusions acting as mitigation process offered limited improvement for the effects of context. On the other hand, the cell level variability due to stress was analyzed. So, it is suggested that the relative variability of a cell is determined by its size and structure, and the variability can be improved to some extent by editing the cells' structure. Based on the analysis of the physical sources and properties of LDE, this paper presents a set of layout guidelines for mitigating layout dependent variability of 40 and 28nm CMOS cell

Managing variability in 40NM and 28NM designs

This article presents a study of variability-aware design methodology that allows designers to lower the risks of silicon failure and to improve their design margins and flows. Supplied by a group of researchers and engineers at CSR, the University of Southampton and Cadence Design Systems