Statistical lifetime analysis of memristive crossbar matrix

Memristors are considered one of the most favorable emerging device alternatives for future memory technologies. They are attracting great attention recently, due to their high scalability and compatibility with CMOS fabrication process. Alongside their benefits, they also face reliability concerns (e.g. manufacturing variability). In this sense our work analyzes key sources of uncertainties in the operation of the memristive memory and we present an analytic approach to predict the expected lifetime distribution of a memristive crossbar.Postprint (published version

RRAM variability and its mitigation schemes

Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.Peer ReviewedPostprint (author's final draft

Memcapacitive Devices in Logic and Crossbar Applications

Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about 7x less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about 1,500x for the MNIST dataset and a factor of about 1,000x for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective

On metrics of density and power efficiency, neuromorphic technologies have the potential to surpass mainstream computing technologies in tasks where real-time functionality, adaptability, and autonomy are essential. While algorithmic advances in neuromorphic computing are proceeding successfully, the potential of memristors to improve neuromorphic computing have not yet born fruit, primarily because they are often used as a drop-in replacement to conventional memory. However, interdisciplinary approaches anchored in machine learning theory suggest that multifactor plasticity rules matching neural and synaptic dynamics to the device capabilities can take better advantage of memristor dynamics and its stochasticity. Furthermore, such plasticity rules generally show much higher performance than that of classical Spike Time Dependent Plasticity (STDP) rules. This chapter reviews the recent development in learning with spiking neural network models and their possible implementation with memristor-based hardware

Reliability-aware memory design using advanced reconfiguration mechanisms

Fast and Complex Data Memory systems has become a necessity in modern computational units in today's integrated circuits. These memory systems are integrated in form of large embedded memory for data manipulation and storage. This goal has been achieved by the aggressive scaling of transistor dimensions to few nanometer (nm) sizes, though; such a progress comes with a drawback, making it critical to obtain high yields of the chips. Process variability, due to manufacturing imperfections, along with temporal aging, mainly induced by higher electric fields and temperature, are two of the more significant threats that can no longer be ignored in nano-scale embedded memory circuits, and can have high impact on their robustness. Static Random Access Memory (SRAM) is one of the most used embedded memories; generally implemented with the smallest device dimensions and therefore its robustness can be highly important in nanometer domain design paradigm. Their reliable operation needs to be considered and achieved both in cell and also in architectural SRAM array design. Recently, and with the approach to near/below 10nm design generations, novel non-FET devices such as Memristors are attracting high attention as a possible candidate to replace the conventional memory technologies. In spite of their favorable characteristics such as being low power and highly scalable, they also suffer with reliability challenges, such as process variability and endurance degradation, which needs to be mitigated at device and architectural level. This thesis work tackles such problem of reliability concerns in memories by utilizing advanced reconfiguration techniques. In both SRAM arrays and Memristive crossbar memories novel reconfiguration strategies are considered and analyzed, which can extend the memory lifetime. These techniques include monitoring circuits to check the reliability status of the memory units, and architectural implementations in order to reconfigure the memory system to a more reliable configuration before a fail happens.Actualmente, el diseño de sistemas de memoria en circuitos integrados busca continuamente que sean más rápidos y complejos, lo cual se ha vuelto de gran necesidad para las unidades de computación modernas. Estos sistemas de memoria están integrados en forma de memoria embebida para una mejor manipulación de los datos y de su almacenamiento. Dicho objetivo ha sido conseguido gracias al agresivo escalado de las dimensiones del transistor, el cual está llegando a las dimensiones nanométricas. Ahora bien, tal progreso ha conllevado el inconveniente de una menor fiabilidad, dado que ha sido altamente difícil obtener elevados rendimientos de los chips. La variabilidad de proceso - debido a las imperfecciones de fabricación - junto con la degradación de los dispositivos - principalmente inducido por el elevado campo eléctrico y altas temperaturas - son dos de las más relevantes amenazas que no pueden ni deben ser ignoradas por más tiempo en los circuitos embebidos de memoria, echo que puede tener un elevado impacto en su robusteza final. Static Random Access Memory (SRAM) es una de las celdas de memoria más utilizadas en la actualidad. Generalmente, estas celdas son implementadas con las menores dimensiones de dispositivos, lo que conlleva que el estudio de su robusteza es de gran relevancia en el actual paradigma de diseño en el rango nanométrico. La fiabilidad de sus operaciones necesita ser considerada y conseguida tanto a nivel de celda de memoria como en el diseño de arquitecturas complejas basadas en celdas de memoria SRAM. Actualmente, con el diseño de sistemas basados en dispositivos de 10nm, dispositivos nuevos no-FET tales como los memristores están atrayendo una elevada atención como posibles candidatos para reemplazar las actuales tecnologías de memorias convencionales. A pesar de sus características favorables, tales como el bajo consumo como la alta escabilidad, ellos también padecen de relevantes retos de fiabilidad, como son la variabilidad de proceso y la degradación de la resistencia, la cual necesita ser mitigada tanto a nivel de dispositivo como a nivel arquitectural. Con todo esto, esta tesis doctoral afronta tales problemas de fiabilidad en memorias mediante la utilización de técnicas de reconfiguración avanzada. La consideración de nuevas estrategias de reconfiguración han resultado ser validas tanto para las memorias basadas en celdas SRAM como en `memristive crossbar¿, donde se ha observado una mejora significativa del tiempo de vida en ambos casos. Estas técnicas incluyen circuitos de monitorización para comprobar la fiabilidad de las unidades de memoria, y la implementación arquitectural con el objetivo de reconfigurar los sistemas de memoria hacia una configuración mucho más fiables antes de que el fallo suced

An Analytical Approach for Memristive Nanoarchitectures

As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nano-features and unique $I$-$V$ characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and hence provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.Comment: 12 pages, 10 figures, 4 table

Simulation and implementation of novel deep learning hardware architectures for resource constrained devices

Corey Lammie designed mixed signal memristive-complementary metal–oxide–semiconductor (CMOS) and field programmable gate arrays (FPGA) hardware architectures, which were used to reduce the power and resource requirements of Deep Learning (DL) systems; both during inference and training. Disruptive design methodologies, such as those explored in this thesis, can be used to facilitate the design of next-generation DL systems

Tailored electrical characteristics in multilayer metal-oxide-based-memristive devices

Auf Mehrlagen-Metalloxiden basierende memristive Bauelemente sind einer der vielversprechendsten Kandidaten für neuromorphes Computing. Allerdings stellen spezifische Anwendungen des neuromorphen Computings unterschiedliche Anforderungen an die memristiven Bauelemente. Eine ungelöste Herausforderung in der technologischen Entwicklung ist daher das maßgeschneiderte Design von memristiven Bauelementen für spezifische Anwendungen. Insbesondere die unterschiedlichen Materialien des Schichtstapels erschweren die Herstellungsprozesse aufgrund einer großen Anzahl von Parametern, wie z. B. der Stapelsequenzen und -dicken und der Qualität sowie der Eigenschaften der einzelnen Schichten. Daher sind systematische Untersuchungen der einzelnen Bauelementparameter besonders entscheidend. Darüber hinaus müssen sie mit einem tiefgreifenden Verständnis der zugrundeliegenden physikalischen Prozesse kombiniert werden, um die Lücke zwischen Materialdesign und elektrischen Eigenschaften der resultierenden memristiven Bauelemente zuschließen. Um memristive Bauelemente mit unterschiedlichen resistiven Schalteigenschaften zu erhalten, werden verschiedene Abfolgen und Kombinationen von drei Metalloxidschichten (TiOx, HfOx, und AlOx) hergestellt und untersucht. Zunächst werden einschichtige Oxidbauelemente untersucht, um Kandidaten für mehrschichtige Stapel zu identifizieren. Zweitens werden zweischichtige TiOx/HfOx Oxidbauelemente hergestellt. Anhand von systematischen Experimenten und statistischen Analysen wird gezeigt, dass die Stöchiometrie, die Dicke, und die Fläche des Bauelements die Betriebsspannungen, die Nichtlinearität beim resistiven Schalten und die Variabilität beeinflussen. Drittens werden TiOx/AlOx/HfOx-basierte Bauelemente hergestellt. Durch das Hinzufügen von AlOx in die zweischichtigen Oxidstapel weisen diese dreischichtigen Bauelemente optimale elektrische Eigenschaften für den Einsatz in neuromorpher Hardware auf, wie z. B. elektroformierungsfreies und strombegrenzungsloses Schalten sowie eine lange Lebensdauer. Die entwickelten memristiven Bauelemente werden in Systeme, wie Kreuzpunkt-Strukturen und Ein-Transistor-ein-Memristor-Konfigurationen integriert. Hier wird die Eignung für effizientes neuromorphes Computing bewertet. Außerdem werden Methoden zur stufenlosen analogen Einstellung des Widerstands der Bauelemente demonstriert. Diese Eigenschaft ermöglicht effiziente neuromorphe Rechenschemata. Diese umfassende Studie beleuchtet die Beziehung zwischen den Bauelementparametern und den elektrischen Eigenschaften von mehrschichtigen memristiven Bauelementen auf Metalloxidbasis. Auf dieser Grundlage werden maßgeschneiderte Methoden für spezifische neuromorphe Anwendungen entwickelt.Multilayer metal-oxide-based-memristive devices are one of the most promising candidates for neuromorphic computing. However, specific applications of neuromorphic computing call for different requirements for memristive devices. Therefore, an open challenge in technological development is the tailored design of memristive devices for specific applications. In particular, multilayer stacks complicate fabrication processes due to a large number of device parameters such as staking sequences and thicknesses, quality, and property of each layer. Therefore, systematic investigations of the individual device parameters are particularly decisive. Moreover, they need to be combined with a profound understanding of the underlying physical processes to bridge the gap between material design and electrical characteristics of the resulting memristive devices. To obtain memristive devices with different resistance switching characteristics, various sequences and combinations of three metal oxide layers (TiOx, HfOx, and AlOx) are fabricated and studied. First, single-layer oxide devices are investigated to find desirable multilayer stacks for memristive devices. Second, TiOx/HfOx-based bilayer oxide devices are fabricated. Via systematic experiments and statistical analysis, it is shown that the stoichiometry, thickness, and device area influence operating voltages, non-linearity in resistive switching, and variability. Third, TiOx/AlOx/HfOx-based devices are fabricated. By adding AlOx into the bilayer oxide stacks, these trilayer devices present favorable electrical features for use in neuromorphic hardware, such as electroforming-free and compliance-free switching as well as long retention. The developed memristive devices are integrated into systems such as crossbar structures and one-transistor-one-memristor configurations. Here, suitability for efficient neuromorphic computing is assessed. Also, methods to tune the device resistance gradually in an analog fashion are demonstrated. This feature allows for efficient neuromorphic computation. This comprehensive study highlights the relationship between device parameters and electrical properties of multilayer metal-oxide-based memristive devices. On this basis, tailoring methodologies are established for specific neuromorphic applications