A comprehensive comparison of voltage and current control techniques for three-phase VSI converters

Converting electrical energy from direct current to alternate current, or vice versa, is one of the most frequently performed tasks in today’s electrical systems. The Voltage Source Inverter (VSI) is the most widely used topology to accomplish this task. This paper compares the performance of three control algorithms for voltage source inverter (VSI) with PI, PR and MP control algorithms were applied for voltage control and current control. For voltage control the VSI synthesizes the sinusoidal voltage system for an islanded application. In current control the VSI injects energy into the power grid by synthesizing sinusoidal currents. A general comparison is made of the performance of the three control algorithms under the presented conditions, helping to choose the control algorithm to use in a given application.This work has been supported by FCT – Fundação para a Ciência e Tecnologia within the Project Scope: UIDB/00319/2020. This work has been supported by the FCT Project QUALITY4POWER PTDC/EEI-EEE/28813/2017, and by the FCT Project DAIPESEV PTDC/EEI-EEE/30382/2017. Mr. Luis A. M. Barros is supported by the doctoral scholarship PD/BD/143006/2018 granted by the Portuguese FCT foundation

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Power Electronics and Energy Management for Battery Storage Systems

The deployment of distributed renewable generation and e-mobility systems is creating a demand for improved dynamic performance, flexibility, and resilience in electrical grids. Various energy storages, such as stationary and electric vehicle batteries, together with power electronic interfaces, will play a key role in addressing these requests thanks to their enhanced functionality, fast response times, and configuration flexibility. For the large-scale implementation of this technology, the associated enabling developments are becoming of paramount importance. These include energy management algorithms; optimal sizing and coordinated control strategies of different storage technologies, including e-mobility storage; power electronic converters for interfacing renewables and battery systems, which allow for advanced interactions with the grid; and increase in round-trip efficiencies by means of advanced materials, components, and algorithms. This Special Issue contains the developments that have been published b researchers in the areas of power electronics, energy management and battery storage. A range of potential solutions to the existing barriers is presented, aiming to make the most out of these emerging technologies

Combinación de clasificadores: construcción de características e incremento de la diversidad

Los multiclasificadores son actualmente un área de interés dentro del Reconocimiento de Patrones. En esta tesis se presentan tres métodos multiclasificadores: "Cascadas para datos nominales", "Disturbing Neighbors" y "Random Feature Weights". Las Cascadas permiten que clasificadores que necesitan entradas numéricas mejoren sus resultados, tomando como entradas adicionales las estimaciones de probabilidad de otro clasificador que sí pueda trabajar con datos nominales. "Disturbing Neighbors" aumenta el conjunto de entrenamiento de cada clasificador base a partir de la salida de un clasificador NN. El NN de cada clasificador base es obtenido de forma aleatoria. Random Feature Weights es un método que utiliza árboles cómo clasificadores base, que modifica la función de mérito de los mismos mediante un peso aleatorio. Además la tesis aporta nuevos diagramas para la visualización de la diversidad de los clasificadores base: Diagramas de Movimiento Kappa-Error y los Diagramas de Movimiento Relativo Kappa-Erro

Desenvolvimento do condicionador série e um iUPQC com interface otimizada com energias renováveis aplicado a uma microrrede

Dissertação de mestrado em Engenharia Eletrónica Industrial e ComputadoresA qualidade de energia elétrica (QEE) tornou-se um fator importante nos sistemas elétricos atuais. Estudos comprovam que instalações elétricas com problemas de QEE podem registar prejuízos económicos avultados. Outra das grandes apostas da comunidade científica atual são os sistemas de produção de energia baseados em fontes de energia renovável. Estes atingiram uma grande relevância dados os problemas ambientais vividos, sendo uma das opções de produção de energia elétrica em detrimento da queima de combustíveis fósseis. Assim, o tema desta dissertação de mestrado vem ao encontro destas duas vertentes, integrando produção de energia a partir de sistemas fotovoltaicos e conversores capazes de mitigar problemas de QEE. Atualmente, existem diversos equipamentos capazes de mitigar alguns problemas de QEE como condicionadores ativos de potência ou fontes de alimentação ininterrupta (Uninterruptible Power Supply - UPS). Contudo, existe um equipamento capaz de mitigar a maioria dos problemas de QEE, sendo este o Condicionador Unificado de Qualidade de Energia Elétrica (UPQC). Este equipamento é composto por um condicionador ativo paralelo e um condicionador ativo série que partilham o mesmo barramento CC. Nesta dissertação de mestrado é descrito o desenvolvimento de um condicionador ativo série integrado num Condicionador Unificado de Qualidade de Energia com Controlo Invertido (iUPQC) com interface otimizada com energias renováveis aplicado a uma microrrede. O iUPQC é um equipamento usado para mitigação de problemas de QEE, com a particularidade de possuir controlo invertido em relação ao UPQC. O condicionador ativo série controla a corrente da rede enquanto o condicionador ativo paralelo controla a tensão das cargas. A integração de conversores de interface com sistemas solares fotovoltaicos e de conversores de interface com sistemas de armazenamento de energia torna esta solução interessante na aplicação em microrredes.Power Quality (PQ) has become an important factor in current electrical systems. Many studies prove that electrical facilities with PQ problems can register considerable economic losses. Another of the great bets of the current scientific community are energy production systems based on renewable energy sources. These reached a great source because of the environmental problems experienced, being one of the options to produce electric energy in detriment of the burning of fossil fuels. The theme of this master dissertation meets these two aspects, integrating energy production from photovoltaic systems and conditioners capable of solve PQ problems. Currently, there are several equipment capable of mitigating some PQ problems such as active power filters or Uninterruptible Power Supply (UPS). However, there is an equipment capable of mitigating most PQ problems, which is the Unified Power Quality Conditioner (UPQC). This is composed of a shunt active conditioner and a series active conditioner that share the same DC bus. This master dissertation describes the development of a series active conditioner integrated into a Unified Power Quality Conditioner with Inverted Control (iUPQC) with an optimized interface with renewable energies applied to a microgrid. The iUPQC is equipment used to mitigate PQ problems, with the particularity of having an inverted control compared to the UPQC. The series active conditioner controls the power grid currents while the shunt active conditioner controls the load voltages. The integration of photovoltaic systems interface converters with energy storage systems makes this solution interesting for microgrids applications.Este trabalho de dissertação está enquadrado no projeto IC&DT “Quality4Power – Enhancing the Power Quality for Industry 4.0 in the era of Microgrids”, financiado pela Fundação para a Ciência e Tecnologia, com a referência PTDC/EEI-EEE/28813/201

Quadratic boosting

This paper presents a strategy to improve the AdaBoost algorithm with a quadratic combination of base classifiers. We observe that learning this combination is necessary to get better performance and is possible by constructing an intermediate learner operating on the combined linear and quadratic terms. This is not trivial, as the parameters of the base classifiers are not under direct control, obstructing the application of direct optimization. We propose a new method realizing iterative optimization indirectly. First we train a classifier by randomizing the labels of training examples. Subsequently, the input learner is called repeatedly with a systematic update of the labels of the training examples in each round. We show that the quadratic boosting algorithm converges under the condition that the given base learner minimizes the empirical error. We also give an upper bound on the VC-dimension of the new classifier. Our experimental results on 23 standard problems show that quadratic boosting compares favorably with AdaBoost on large data sets at the cost of training speed. The classification time of the two algorithms, however, is equivalent

Quadratic boosting

This paper presents a strategy to improve the AdaBoost algorithm with a quadratic combination of base classifiers. We observe that learning this combination is necessary to get better performance and is possible by constructing an intermediate learner operating on the combined linear and quadratic terms. This is not trivial, as the parameters of the base classifiers are not under direct control, obstructing the application of direct optimization. We propose a new method realizing iterative optimization indirectly. First we train a classifier by randomizing the labels of training examples. Subsequently, the input learner is called repeatedly with a systematic update of the labels of the training examples in each round. We show that the quadratic boosting algorithm converges under the condition that the given base learner minimizes the empirical error. We also give an upper bound on the VC-dimension of the new classifier. Our experimental results on 23 standard problems show that quadratic boosting compares favorably with AdaBoost on large data sets at the cost of training speed. The classification time of the two algorithms, however, is equivalent