Heterogeneity-aware scheduling and data partitioning for system performance acceleration

Over the past decade, heterogeneous processors and accelerators have become increasingly prevalent in modern computing systems. Compared with previous homogeneous parallel machines, the hardware heterogeneity in modern systems provides new opportunities and challenges for performance acceleration. Classic operating systems optimisation problems such as task scheduling, and application-specific optimisation techniques such as the adaptive data partitioning of parallel algorithms, are both required to work together to address hardware heterogeneity. Significant effort has been invested in this problem, but either focuses on a specific type of heterogeneous systems or algorithm, or a high-level framework without insight into the difference in heterogeneity between different types of system. A general software framework is required, which can not only be adapted to multiple types of systems and workloads, but is also equipped with the techniques to address a variety of hardware heterogeneity. This thesis presents approaches to design general heterogeneity-aware software frameworks for system performance acceleration. It covers a wide variety of systems, including an OS scheduler targeting on-chip asymmetric multi-core processors (AMPs) on mobile devices, a hierarchical many-core supercomputer and multi-FPGA systems for high performance computing (HPC) centers. Considering heterogeneity from on-chip AMPs, such as thread criticality, core sensitivity, and relative fairness, it suggests a collaborative based approach to co-design the task selector and core allocator on OS scheduler. Considering the typical sources of heterogeneity in HPC systems, such as the memory hierarchy, bandwidth limitations and asymmetric physical connection, it proposes an application-specific automatic data partitioning method for a modern supercomputer, and a topological-ranking heuristic based schedule for a multi-FPGA based reconfigurable cluster. Experiments on both a full system simulator (GEM5) and real systems (Sunway Taihulight Supercomputer and Xilinx Multi-FPGA based clusters) demonstrate the significant advantages of the suggested approaches compared against the state-of-the-art on variety of workloads."This work is supported by St Leonards 7th Century Scholarship and Computer Science PhD funding from University of St Andrews; by UK EPSRC grant Discovery: Pattern Discovery and Program Shaping for Manycore Systems (EP/P020631/1)." -- Acknowledgement

Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters

This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.Ministerio de Economía y Competitividad TEC2016-78430-RFondo Nacional de Investigación de Qatar NPRP 9-310-2-13

Implementation of ANN Controller Based UPQC Integrated with Microgrid

This study discusses how to increase power quality by integrating a unified power quality conditioner (UPQC) with a grid-connected microgrid for clean and efficient power generation. An Artificial Neural Network (ANN) controller for a voltage source converter-based UPQC is proposed to minimize the system’s cost and complexity by eliminating mathematical operations such as a-b-c to d-q-0 translation and the need for costly controllers such as DSPs and FPGAs. In this study, nonlinear unbalanced loads and harmonic supply voltage are used to assess the performance of PV-battery-UPQC using an ANN-based controller. Problems with voltage, such as sag and swell, are also considered. This work uses an ANN control system trained with the Levenberg-Marquardt backpropagation technique to provide effective reference signals and maintain the required dc-link capacitor voltage. In MATLAB/Simulink software, simulations of PV-battery-UPQC employing SRF-based control and ANN-control approaches are performed. The findings revealed that the proposed approach performed better, as presented in this paper. Furthermore, the influence of synchronous reference frame (SRF) and ANN controller-based UPQC on supply currents and the dc-link capacitor voltage response is studied. To demonstrate the superiority of the suggested controller, a comparison of percent THD in load voltage and supply current utilizing SRF-based control and ANN control methods is shown

Analytical Modeling of High Performance Reconfigurable Computers: Prediction and Analysis of System Performance.

The use of a network of shared, heterogeneous workstations each harboring a Reconfigurable Computing (RC) system offers high performance users an inexpensive platform for a wide range of computationally demanding problems. However, effectively using the full potential of these systems can be challenging without the knowledge of the system’s performance characteristics. While some performance models exist for shared, heterogeneous workstations, none thus far account for the addition of Reconfigurable Computing systems. This dissertation develops and validates an analytic performance modeling methodology for a class of fork-join algorithms executing on a High Performance Reconfigurable Computing (HPRC) platform. The model includes the effects of the reconfigurable device, application load imbalance, background user load, basic message passing communication, and processor heterogeneity. Three fork-join class of applications, a Boolean Satisfiability Solver, a Matrix-Vector Multiplication algorithm, and an Advanced Encryption Standard algorithm are used to validate the model with homogeneous and simulated heterogeneous workstations. A synthetic load is used to validate the model under various loading conditions including simulating heterogeneity by making some workstations appear slower than others by the use of background loading. The performance modeling methodology proves to be accurate in characterizing the effects of reconfigurable devices, application load imbalance, background user load and heterogeneity for applications running on shared, homogeneous and heterogeneous HPRC resources. The model error in all cases was found to be less than five percent for application runtimes greater than thirty seconds and less than fifteen percent for runtimes less than thirty seconds. The performance modeling methodology enables us to characterize applications running on shared HPRC resources. Cost functions are used to impose system usage policies and the results of vii the modeling methodology are utilized to find the optimal (or near-optimal) set of workstations to use for a given application. The usage policies investigated include determining the computational costs for the workstations and balancing the priority of the background user load with the parallel application. The applications studied fall within the Master-Worker paradigm and are well suited for a grid computing approach. A method for using NetSolve, a grid middleware, with the model and cost functions is introduced whereby users can produce optimal workstation sets and schedules for Master-Worker applications running on shared HPRC resources

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Exploring manycore architectures for next-generation HPC systems through the MANGO approach

[EN] The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated.This project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671668.Flich Cardo, J.; Agosta, G.; Ampletzer, P.; Atienza-Alonso, D.; Brandolese, C.; Cappe, E.; Cilardo, A.... (2018). Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocessors and Microsystems. 61:154-170. https://doi.org/10.1016/j.micpro.2018.05.011S1541706

Direct current control for grid connected multilevel inverters

Control schemes for inverters of different topologies and various numbers of voltage levels are of great interest for many standard as well as special applications. This thesis describes a novel, robust and high-dynamic direct current control scheme for multilevel voltage source inverters. lt is highly independent from load parameters and universally applicable. The new control method is examined and validated with real measurements . The aim of the thesis is to establish and prove a new concept of a direct current control algorithm for multilevel inverter topologies for grid connected systems. This application is characterized by unknown grid conditions including failure modes and other distortions, complex inverter topologies and a large variety and complexity of current control algorithms for multilevel inverters. Therefore the complexity of the system needs to be reduced. Additionally , the advantages of multilevel inverters and the dynamic performance and robustness of direct current control techniques shall be combined. Starting from a detailed literature study on inverter topologies and direct as well as indirect current control methods, the thesis includes three chapters containing relevant contributions to the achievement of the objectives. A method reducing the control-complexity of multilevel converters has been developed. The simplification method is based on a transformation that converts any three-phase voltage (or current) into a non-orthogonal coordinate system. This choice minimizes the complexity and effort to determine the location of those discrete voltage space vectors directly surrounding the required reference voltage vector. A further improvement is achieved by scaling all coordinates to integer values. This is advantageous for further calculations on microprocessors or FPGA based control systems. The main contribution of this thesis is a new direct current control method minimizing the disadvantages of existing direct methods. At the same time advantages of other control algorithms shall be applied. The new method is based on a simple mathematical equation, that is, the solution of a scalar product, to always select the one inverter output voltage vector best reducing the actual current error. This results in the designation "Scalar Hysteresis Control - SHC". An advanced seeking algorithm ensures robust current control capability even in case of unknown, unsymmetrical or changing loads, in case of rapid set-point changes or in cases of unknown phase voltages . The new method therefore shows excellent properties in terms of simplicity , robustness, dynamics and independence from the inverter level count and the hardware topology . The properties of the control method are verified by means of simulations and real measurements on two-, three- and five-level inverters over the complete voltage operating range. Finally, all contributions are collected together and assessed with regard to the objectives. From the proposed control method new opportunities for future work, further developments and extensions are evolving for continuing scientific researchEls sistemes de control d'inversors de diferents topologies i diferent varis nivells de tensió són de gran interès per moltes aplicacions estàndard i també per aplicacions especials. Aquesta tesi investiga sobre un mètode de control directe de corrent per convertidors multinivell en font de tensió que es mostra robust i presenta una elevada dinàmica en el control de corrent. El mètode és molt robust davant de canvies als paràmetres de la càrrega i aplicable a qualsevol tipus de convertidor. En aquesta tesi s'analitza el mètode i es valida mitjançant resultats experimentals. L'objectiu d'aquesta tesi és establir i demostrar un nou de mètode i algorisme de control directe de corrent aplicat especialment a inversors connectats a la xarxa. L'aplicació es caracteritza per la desconeixença dels paràmetres de la xarxa, incloent diferents modes de falla i distorsions en la seva tensió i una varietat de tipologies de convertidors multinivell. El mètode de control busca simplificar l'algorisme i que pugui ser aplicat en aquest entorn de forma robusta, de forma que es pugui estendre l'ús dels convertidors multinivell sense afegir més complexitat als algorismes de control i modulació. La tesi aborda el problema iniciant amb un anàlisi de la literatura existent en aquest tipus de mètodes de control directe i indirecte del corrent i els convertidors multinivell, per continuar amb l'anàlisi del mètode proposat i la seva demostració mitjançant resultats de simulacions i experimentals. El mètode de simplificació està basat en una transformació que transforma qualsevol sistema trifàsic a un sistema de coordenades no-ortogonal. Escollir aquest sistema de coordenades redueix la complexitat i l'esforç per determinar la ubicació d'aquells vectors espacials que directament envolten el vector de referencia. A més, totes les coordenades s'escalen a valors enters, que permet la programació de l'algorisme en sistemes de control basats en microprocessadors o FPGAs. La principal contribució d'aquesta tesi és un nou mètode de control de corrent que intenta minimitzar els desavantatges dels mètodes indirectes existents a l'actualitat, al mateix moment que s'intenta incorporar els avantatges dels mètodes indirectes. El mètode proposat es basa en una equació matemàtica simple, la solució d'un producte escalar, per trobar el vector de tensió espacial que minimitza l'error de corrent, en el que s'anomena "Scalar Hysteresis Control" o SHC. L'algorisme assegura un control robust del corrent sense la necessitat de conèixer la tensió de fase, o les càrregues, tant si són desequilibrades o canviants. També presenta una dinàmica molt elevada en cas de canvies en la referència. El nou mètode mostra unes propietats excel·lents en termes de simplicitat, robustesa, dinàmica i independència de la tipologia del convertidor i, en el cas de convertidors multinivell, del nombre de nivells. Les propietats del mètode de control són verificades mitjançant simulacions i resultats experimentals en convertidors de dos, tres i fins a cinc nivells de tensió en tot el rang d'operació, fins i tot en la zona de sobremodulació. A partir del mètode de control proposat, s'estan desenvolupant noves aplicacions i extensions, continuant també la contribució a la recerca científica