Двойное кодирование состояний в совмещенном автомате

Предложен метод уменьшения аппаратурных затрат в схеме совмещенного микропрограммного автомата, реализуемого в базисе FPGA. Метод основан на разбиении множества состояний на классы, каждый из которых соответствует отдельному блоку схемы. Такой подход приводит к схемам с регулярной структурой и тремя логическими уровнями. Приведен пример синтеза схемы автомата с использованием предложенного метода. Показаны условия его применения.У статті запропоновано метод зменшення апаратурних витрат при розробці пристроїв управління цифрових систем. Зниження витрат апаратури дозволяє підвищити якість цифрової системи за рахунок зменшення площі кристала НВІС, зниження споживання енергії та підвищення швидкодії. Метод заснований на розбитті множини станів автомата на класи, кожен з яких відповідає окремому блоку схеми. Такий підхід призводить до схем з регулярною структурою і трьома логічними рівнями. У статті наведено приклад синтезу схеми автомата з використанням запропонованого методу. Показані умови його застосування.The article proposes a method of reducing hardware costs in the development of control devices for digital systems. Reducing hardware costs can improve the quality of a digital system by reducing the size of the VLSI chip, reducing energy consumption and increasing speed. The method is based on splitting the set of states of an automaton into classes, each of which corresponds to a separate block of the circuit. This approach leads to circuit with a regular structure having three levels of logic. The article provides an example of the synthesis of an automaton circuit using the proposed method. The conditions of its application are shown

Decomposition and encoding of finite state machines for FPGA implementation

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Generic low power reconfigurable distributed arithmetic processor

Higher performance, lower cost, increasingly minimizing integrated circuit components, and higher packaging density of chips are ongoing goals of the microelectronic and computer industry. As these goals are being achieved, however, power consumption and flexibility are increasingly becoming bottlenecks that need to be addressed with the new technology in Very Large-Scale Integrated (VLSI) design. For modern systems, more energy is required to support the powerful computational capability which accords with the increasing requirements, and these requirements cause the change of standards not only in audio and video broadcasting but also in communication such as wireless connection and network protocols. Powerful flexibility and low consumption are repellent, but their combination in one system is the ultimate goal of designers. A generic domain-specific low-power reconfigurable processor for the distributed arithmetic algorithm is presented in this dissertation. This domain reconfigurable processor features high efficiency in terms of area, power and delay, which approaches the performance of an ASIC design, while retaining the flexibility of programmable platforms. The architecture not only supports typical distributed arithmetic algorithms which can be found in most still picture compression standards and video conferencing standards, but also offers implementation ability for other distributed arithmetic algorithms found in digital signal processing, telecommunication protocols and automatic control. In this processor, a simple reconfigurable low power control unit is implemented with good performance in area, power and timing. The generic characteristic of the architecture makes it applicable for any small and medium size finite state machines which can be used as control units to implement complex system behaviour and can be found in almost all engineering disciplines. Furthermore, to map target applications efficiently onto the proposed architecture, a new algorithm is introduced for searching for the best common sharing terms set and it keeps the area and power consumption of the implementation at low level. The software implementation of this algorithm is presented, which can be used not only for the proposed architecture in this dissertation but also for all the implementations with adder-based distributed arithmetic algorithms. In addition, some low power design techniques are applied in the architecture, such as unsymmetrical design style including unsymmetrical interconnection arranging, unsymmetrical PTBs selection and unsymmetrical mapping basic computing units. All these design techniques achieve extraordinary power consumption saving. It is believed that they can be extended to more low power designs and architectures. The processor presented in this dissertation can be used to implement complex, high performance distributed arithmetic algorithms for communication and image processing applications with low cost in area and power compared with the traditional methods

Synthesis and simulation of reprogrammable control units from hierarchical specifications

Doutoramento em Engenharia ElectrotécnicaAs máquinas finitas de estados (FSM) têm sido usadas para especificar e implementar unidades de controlo e têm sido um assunto de grande importância nas últimas cinco décadas. Devido ao aumento da complexidade das unidades de controlo e uma vez que o modelo FSM não permite descrições hierárquicas e concorrentes, novos modelos formais que suportam hierarquia e concorrência têm sido propostos com o objectivo de ultrapassar as limitações do modelo FSM e que permitem a especificação de unidades de controlo complexas usando uma metodologia de decomposição hierarquizada. Apesar disso não têm sido propostas arquitecturas de máquinas finitas de estados hierárquicas, com excepção das máquinas construídas com memória stack, que possam ser vistas como uma máquina integral que implementa internamente e de forma eficiente a transição entre os diferentes níveis hierárquicos da máquina. Esta tese aborda a síntese de máquinas de estados especificadas hierarquicamente e propõe duas arquitecturas de máquinas hierárquicas (HFSM) e uma máquina paralela hierárquica (PHFSM) contruídas com memória stack, que são flexíveis, extensíveis e reutilizáveis. Apresenta também, a metodologia de síntese lógica que permite construir a tabela de transição de estados a partir da especificação hierárquica, tabela essa que é utilizada na implementação dos modelos propostos. Considerando que é altamente recomendável a utilização de modelos formais que permitam descrições hierárquicas e concorrentes na especificação de unidades de controlo complexas, os modelos de grafos hierárquicos (HGS) e grafos paralelos hierárquicos (PHGS) são apresentados e são feitas algumas considerações acerca da sua utilização, execução e correcção. É ainda explicado como se pode validar a especificação hierárquica da funcionalidade de unidades de controlo complexas através da verificação automática e simulação da especificação baseada em HGSs. Os modelos propostos de máquinas de estados são apresentados detalhadamente tendo em atenção o seu funcionamento, implementação interna baseada em memórias e sincronização, bem como as novas facilidades de flexibilidade e extensibilidade que estes modelos apresentam. É apresentada a metodologia manual da síntese lógica que é necessário implementar a partir das especificações hierárquicas baseadas em HGSs ou PHGSs de forma a construir a tabela de transição de estados que especifica a máquina hierárquica ou paralela hierárquica, para as máquinas de estados de Moore, Mealy ou mista Moore/Mealy. É também apresentado um programa que implementa automaticamente a síntese lógica dos dois modelos de máquinas de estados hierárquicas propostos a partir da especificação feita com HGSs. Os modelos de arquitecturas propostas, bem como a metodologia de síntese, foram validadas através de uma simulação em VHDL que foi feita usando as ferramentas de simulação da Synopsys.Finite state machines (FSM) have been a topic of great importance in the last five decades and have been used to specify and implement control units. Due to the increasing complexity of control units and since the FSM model does not explicitly support hierarchy and concurrency, new state-based models with hierarchical and concurrent constructions were proposed in order to overcome the limitations of the conventional FSM model and allowing the specification of complex control units in a top-down manner. Still, there are not many hierarchical FSM architectures (HFSM) that have been proposed to implement those hierarchical specifications and most of them cannot be seen as a whole FSM implementing internally in an efficient way the switching between the different hierarchical levels of the machine, except for the HFSM with stack memory. This thesis tackles the synthesis of FSMs from hierarchical specifications and proposes two HFSMs and a parallel hierarchical FSM (PHFSM) with stack memory that can provide such facilities as flexibility, extensibility and reusability. It also presents the synthesis methodology from hierarchical specifications to the generation of state transition tables that can be used to carry out the logic synthesis of the proposed HFSM models. Considering that the use of formal state-based models that provide hierarchical and concurrent constructions is highly recommended for specifying complex control units, hierarchical graph-schemes (HGS) and parallel hierarchical graphschemes (PHGS) are used and some considerations about their execution and correctness are presented. It is also explained how HGSs can be used to specify a control algorithm and how it is possible to verify automatically its correctness and to validate the intended functionality through simulation. Using the first model of a HFSM with stack memory as a starting model, two new models that can provide flexibility, extensibility and reusability and a PHFSM model that combines hierarchy and pseudo-parallel execution of operations are proposed. Their functionality, flexibility, extensibility, synchronisation and internal realisation are fully explained. To implement a control unit specified with a set of HGSs/PHGSs it is necessary to perform the first step of the sequential logic synthesis, taking in consideration the pretended target model. The manual synthesis methodology required to build the state transition table of a HFSM/PHFSM starting from a hierarchical specification based on HGSs/PHGSs is explained for a Moore, a Mealy and a mixed Moore/Mealy FSM. A tool that automatically performs this first step for the two HFSM models proposed is also presented. In order to validate the proposed HFSM/PHFSM models and their synthesis, the models were described in VHDL for a LUT-based implementation and simulated using the Synopsys simulation tools

A Golden Age of Hardware Description Languages: Applying Programming Language Techniques to Improve Design Productivity

Leading experts have declared that there is an impending golden age of computer architecture. During this age, the rate at which architects will be able to innovate will be directly tied to the design and implementation of the hardware description languages they use. Thus, the programming languages community stands on the critical path to this new golden age. This implies that we are also on the cusp of a golden age of hardware description languages. In this paper, we discuss the intellectual challenges facing researchers interested in hardware description language design, compilers, and formal methods. The major theme will be identifying opportunities to apply programming language techniques to address issues in hardware design productivity. Then, we present a vision for a multi-language system that provides a framework for developing solutions to these intellectual problems. This vision is based on a meta-programmed host language combined with a core embedded hardware description language that is used as the basis for the research and development of a sea of domain-specific languages. Central to the design of this system is the core language which is based on an abstraction that provides a general mechanism for the composition of hardware components described in any language

Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

Evolutionary algorithms for synthesis and optimisation of sequential logic circuits

Considerable progress has been made recently 1n the understanding of combinational logic optimization. Consequently a large number of university and industrial Electric Computing Aided Design (ECAD) programs are now available for optimal logic synthesis of combinational circuits. The progress with sequential logic synthesis and optimization, on the other hand, is considerably less mature. In recent years, evolutionary algorithms have been found to be remarkably effective way of using computers for solving difficult problems. This thesis is, in large part, a concentrated effort to apply this philosophy to the synthesis and optimization of sequential circuits. A state assignment based on the use of a Genetic Algorithm (GA) for the optimal synthesis of sequential circuits is presented. The state assignment determines the structure of the sequential circuit realizing the state machine and therefore its area and performances. The synthesis based on the GA approach produced designs with the smallest area to date. Test results on standard fmite state machine (FS:M) benchmarks show that the GA could generate state assignments, which required on average 15.44% fewer gates and 13.47% fewer literals compared with alternative techniques. Hardware evolution is performed through a succeSSlOn of changes/reconfigurations of elementary components, inter-connectivity and selection of the fittest configurations until the target functionality is reached. The thesis presents new approaches, which combine both genetic algorithm for state assignment and extrinsic Evolvable Hardware (EHW) to design sequential logic circuits. The implemented evolutionary algorithms are able to design logic circuits with size and complexity, which have not been demonstrated in published work. There are still plenty of opportunities to develop this new line of research for the synthesis, optimization and test of novel digital, analogue and mixed circuits. This should lead to a new generation of Electronic Design Automation tools.EThOS - Electronic Theses Online ServiceGBUnited Kingdo