Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog

Center for Aeronautics and Space Information Sciences

This report summarizes the research done during 1991/92 under the Center for Aeronautics and Space Information Science (CASIS) program. The topics covered are computer architecture, networking, and neural nets

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Optimization of DSSS Receivers Using Hardware-in-the-Loop Simulations

Over the years, there has been significant interest in defining a hardware abstraction layer to facilitate code reuse in software defined radio (SDR) applications. Designers are looking for a way to enable application software to specify a waveform, configure the platform, and control digital signal processing (DSP) functions in a hardware platform in a way that insulates it from the details of realization. This thesis presents a tool-based methodolgy for developing and optimizing a Direct Sequence Spread Spectrum (DSSS) transceiver deployed in custom hardware like Field Programmble Gate Arrays (FPGAs). The system model consists of a tranmitter which employs a quadrature phase shift keying (QPSK) modulation scheme, an additive white Gaussian noise (AWGN) channel, and a receiver whose main parts consist of an analog-to-digital converter (ADC), digital down converter (DDC), image rejection low-pass filter (LPF), carrier phase locked loop (PLL), tracking locked loop, down-sampler, spread spectrum correlators, and rectangular-to-polar converter. The design methodology is based on a new programming model for FPGAs developed in the industry by Xilinx Inc. The Xilinx System Generator for DSP software tool provides design portability and streamlines system development by enabling engineers to create and validate a system model in Xilinx FPGAs. By providing hierarchical modeling and automatic HDL code generation for programmable devices, designs can be easily verified through hardware-in-the-loop (HIL) simulations. HIL provides a significant increase in simulation speed which allows optimization of the receiver design with respect to the datapath size for different functional parts of the receiver. The parameterized datapath points used in the simulation are ADC resolution, DDC datapath size, LPF datapath size, correlator height, correlator datapath size, and rectangular-to-polar datapath size. These parameters are changed in the software enviornment and tested for bit error rate (BER) performance through real-time hardware simualtions. The final result presents a system design with minimum harware area occupancy relative to an acceptable BER degradation

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Design and evaluation of a digital processing unit for satellite angular velocity estimation

A satellite's absolute attitude and angular rate are both important measurements for satellite missions that require navigation. Typically, these measurements have been made by separate sensors, with star cameras being used to determine a satellite's absolute attitude, and gyroscopes being used as the primary rate sensors. Recently, there have been multiple efforts to measure both of these quantities using only the star camera, however the work primarily involves solutions where the optical sensor and the unit that processes the images are separate integrated circuits. Operation in this modality requires the use of chip to chip communication in order to estimate angular rate from star tracker images, which can lead to an increase in system power, a degradation in performance, and increased latency. The goal of this thesis is to consolidate the sensing and processing into a single integrated circuit. The design and evaluation of a digital processing unit that estimates angular rate and facilitates the realization of image sensor and processor integration is presented. The processing unit is implemented in UMC's 130 nm process, has an area of 10 mm × 200 μm, and consumes 8.253 mW of power

A computer-aided telescope pointing system utilizing a video star tracker

The Video Inertial Pointing (VIP) System developed to satisfy the acquisition and pointing requirements of astronomical telescopes is described. A unique feature of the system is the use of a single sensor to provide information for the generation of three axis pointing error signals and for a cathode ray tube (CRT) display of the star field. The pointing error signals are used to update the telescope's gyro stabilization and the CRT display is used by an operator to facilitate target acquisition and to aid in manual positioning of the telescope optical axis. A model of the system using a low light level vidicon built and flown on a balloon-borne infrared telescope is briefly described from a state of the art charge coupled device (CCD) sensor. The advanced system hardware is described and an analysis of the multi-star tracking and three axis error signal generation, along with an analysis and design of the gyro update filter, are presented. Results of a hybrid simulation are described in which the advanced VIP system hardware is driven by a digital simulation of the star field/CCD sensor and an analog simulation of the telescope and gyro stabilization dynamics