Plasma damage in floating metal-insulator-metal capacitors

In this paper, charging induced damage (CID) to metal-insulator-metal capacitors (MIMCs), is reported. CID does not necessarily lead to direct yield loss, but may also induce latent damage leading to reliability losses. The damage is caused by the build up of a voltage potential difference between the two plates of the capacitor. A simple logarithmic relation is discovered between the damage by this voltage potential and the ratio of the area of the exposed antennas connected to the plates of the MIMC. This function allows anticipation of damage in MIMCs with long interconnect

OXIDATION OF SILICON - THE VLSI GATE DIELECTRIC

Silicon dominates the semiconductor industry for good reasons. One factor is the stable, easily formed, insulating oxide, which aids high performance and allows practical processing. How well can these virtues survive as new demands are made on integrity, on smallness of feature sizes and other dimensions, and on constraints on processing and manufacturing methods? These demands make it critical to identify, quantify and predict the key controlling growth and defect processes on an atomic scale.The combination of theory and novel experiments (isotope methods, electronic noise, spin resonance, pulsed laser atom probes and other desorption methods, and especially scanning tunnelling or atomic force microscopies) provide tools whose impact on models is just being appreciated. We discuss the current unified model for silicon oxidation, which goes beyond the traditional descriptions of kinetic and ellipsometric data by explicitly addressing the issues raised in isotope experiments. The framework is still the Deal-Grove model, which provides a phenomenology to describe the major regimes of behaviour, and gives a base from which the substantial deviations can be characterized. In this model, growth is limited by diffusion and interfacial reactions operating in series. The deviations from Deal-Grove are most significant for just those first tens of atomic layers of oxide which are critical for the ultra-thin oxide layers now demanded. Several features emerge as important. First is the role of stress and stress relaxation. Second is the nature of the oxide closest to the Si, both its defects and its differences from the amorphous stoichiometric oxide further out, whether in composition, in network topology, or otherwise. Thirdly, we must consider the charge states of both fixed and mobile species. In thin films with very different dielectric constants, image terms can be important; these terms affect interpretation of spectroscopies, the injection of oxidant species and relative defect stabilities. This has added importance now that P-b concentrations have been correlated with interfacial stress. This raises further issues about the perfection of the oxide random network and the incorporation of interstitial species like molecular oxygen.Finally, the roles of contamination, particles, metals, hydrocarbons etc are important, as is interface roughness. These features depend on pre-gate oxide cleaning and define the Si surface that is to be oxidized which may have an influence on the features listed above

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Charging damage in floating metal-insulator-metal capacitors

In this paper, charging induced damage (CID) to metal-insulator-metal capacitors (MIMC) is reported. The damage is caused by the build up of a voltage potential difference between the two plates of the capacitor. A simple logarithmic relation is discovered between the damage by this voltage potential and the ratio of the area of the exposed antennas connected to the plates of the MIMC. This function allows anticipation of damage in MIMC devices with long interconnects. The source of the damage is still the subject of further investigatio

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Development of an ontology supporting failure analysis of surface safety valves used in Oil & Gas applications

Treball desenvolupat dins el marc del programa 'European Project Semester'.The project describes how to apply Root Cause Analysis (RCA) in the form of a Failure Mode Effect and Criticality Analysis (FMECA) on hydraulically actuated Surface Safety Valves (SSVs) of Xmas trees in oil and gas applications, in order to be able to predict the occurrence of failures and implement preventive measures such as Condition and Performance Monitoring (CPM) to improve the life-span of a valve and decrease maintenance downtime. In the oil and gas industry, valves account for 52% of failures in the system. If these failures happen unexpectedly it can cause a lot of problems. Downtime of the oil well quickly becomes an expensive problem, unscheduled maintenance takes a lot of extra time and the lead-time for replacement parts can be up to 6 months. This is why being able to predict these failures beforehand is something that can bring a lot of benefits to a company. To determine the best course of action to take in order to be able to predict failures, a FMECA report is created. This is an analysis where all possible failures of all components are catalogued and given a Risk Priority Number (RPN), which has three variables: severity, detectability and occurrence. Each of these is given a rating between 0 and 10 and then the variables are multiplied with each other, resulting in the RPN. The components with an RPN above an acceptable risk level are then further investigated to see how to be able to detect them beforehand and how to mitigate the risk that they pose. Applying FMECA to the SSV mean breaking the system down into its components and determining the function, dependency and possible failures. To this end, the SSV is broken up into three sub-systems: the valve, the actuator and the hydraulic system. The hydraulic system is the sub-system of the SSV responsible for containing, transporting and pressurizing of the hydraulic fluid and in turn, the actuator. It also contains all the safety features, such as pressure pilots, and a trip system in case a problem is detected in the oil line. The actuator is, as the name implies, the sub-system which opens and closes the valve. It is made up of a number of parts such as a cylinder, a piston and a spring. These parts are interconnected in a number of ways to allow the actuator to successfully perform its function. The valve is the actual part of the system which interacts with the oil line by opening and closing. Like the actuator, this sub-system is broken down into a number of parts which work together to perform its function. After breaking down and defining each subsystem on a functional level, a model was created using a functional block diagram. Each component also allows for the defining of dependencies and interactions between the different components and a failure diagram for each component. This model integrates the three sub-systems back into one, creating a complete picture of the entire system which can then be used to determine the effects of different failures in components to the rest of the system. With this model completed we created a comprehensive FMECA report and test the different possible CPM solutions to mitigate the largest risks