FOSS EKV2.6 Verilog-A Compact MOSFET Model

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice

Modular integrated SiC MOSFET matrix converter

This paper presents the assembly and characterization of an integrated all SiC 3-to-1 phases matrix converter, of typical application in domains requiring harsh environment withstand capability with high reliability and availability levels (e.g., renewable energies, solid-state transformation, smart grids, electric transport). Commercially available silicon-carbide (SiC) power MOSFETs are procured in bare-die form to develop custom-packaged bi-directional switches, with an advanced approach aiming to optimize the electro-thermal and electro-magnetic performance at switch level. Advanced cooling and packaging solutions at system level enable modularity with reduced impact of single component failure on the overall system, contributing to significantly reduced maintenance and repair costs

Analysis of solid state relay solutions based on different semiconductor technologies

This paper provides an analysis on the design, implementation and operation of Bi-Directional Switches (BDS) based on power semiconductor devices intended to replace Electro Mechanical Relays (EMR) in home appliances. Static and dynamic characterizations of test vehicles developed using different power device semiconductor technologies (TRIAC, Super Junction (SJ) MOSFET, IGBT...) are presented. At this time, emerging Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) seem to be very suitable for the mentioned applications. Actually, GaN HEMTs based BDS has demonstrated to be the best solution to replace EMRs, with a high expectation to a significant cost reduction

Compact modelling in RF CMOS technology

With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today, the standard CMOS technology has become a popular choice for realizing radio frequency (RF) applications. The focus of the thesis is on device compact modelling methodologies in RF CMOS. Compact models oriented to integrated circuit (ICs) computer automatic design (CAD) are the key component of a process design kit (PDK) and the bridge between design houses and foundries. In this work, a novel substrate model is proposed for accurately characterizing the behaviour of RF-MOSFETs with deep n-wells (DNW). A simple test structure is presented to directly access the substrate parasitics from two-port measurements in DNWs. The most important passive device in RFIC design in CMOS is the spiral inductor. A 1-pi model with a novel substrate network is proposed to characterize the broadband loss mechanisms of spiral inductors. Based on the proposed 1-pi model, a physics-originated fully-scalable 2-pi model and model parameter extraction methodology are also presented for spiral inductors in this work. To test and verify the developed active and passive device models and model parameter extraction methods, a series of RF-MOSFETs and planar on-chip spiral inductors with different geometries manufactured by employing standard RF CMOS processes were considered. Excellent agreement between the measured and the simulated results validate the compact models and modelling technologies developed in this work

Towards a More Flexible, Sustainable, Efficient and Reliable Induction Cooking: A Power Semiconductor Device Perspective

Esta tesis tiene como objetivo fundamental la mejora de la flexibilidad, sostenibilidad, eficiencia y fiabilidad de las cocinas de inducción por medio de la utilización de dispositivos semiconductores de potencia: Dentro de este marco, existe una funcionalidad que presenta un amplio rango de mejora. Se trata de la función de multiplexación de potencia, la cual pretende resolverse de una manera más eficaz por medio de la sustitución de los comúnmente utilizados relés electromecánicos por dispositivos de estado sólido. De entre todas las posibles implementaciones, se ha identificado entre las más prometedoras a aquellas basadas en dispositivos de alta movilidad de electrones (HEMT) de Nitruro de Galio (GaN) y de aquellas basadas en Carburo de Silicio (SiC), pues presentan unas características muy superiores a los relés a los que se pretende sustituir. Por el contrario, otras soluciones que inicialmente parecían ser muy prometedoras, como los MOSFETs de Súper-Unión, han presentado una serie de comportamientos anómalos, que han sido estudiados minuciosamente por medio de simulaciones físicas a nivel de chip. Además, se analiza en distintas condiciones la capacidad en cortocircuito de dispositivos convencionalmente empleados en cocinas de inducción, como son los IGBTs, tratándose de encontrar el equilibrio entre un comportamiento robusto al tiempo que se mantienen bajas las pérdidas de potencia. Por otra parte, también se estudia la robustez y fiabilidad de varios GaN HEMT de 600- 650 V tanto de forma experimental como por medio de simulaciones físicas. Finalmente se aborda el cálculo de las pérdidas de potencia en convertidores de potencia resonantes empleando técnicas de termografía infrarroja. Por medio de esta técnica no solo es posible medir de forma precisa las diferentes contribuciones de las pérdidas, sino que también es posible apreciar cómo se distribuye la corriente a nivel de chip cuando, por ejemplo, el componente opera en modo de conmutación dura. Como resultado, se obtiene información relevante relacionada con modos de fallo. Además, también ha sido aprovechar las caracterizaciones realizadas para obtener un modelo térmico de simulación.This thesis is focused on addressing a more flexible, sustainable, efficient and reliable induction cooking approach from a power semiconductor device perspective. In this framework, this PhD Thesis has identified the following activities to cover such demands: In view of the growing interest for an effective power multiplexing in Induction Heating (IH) applications, improved and efficient Solid State Relays (SSRs) as an alternative to the electromechanical relays (EMRs) are deeply investigated. In this context, emerging Gallium Nitride (GaN) High‐Electron‐Mobility Transistors (GaN HEMTs) and Silicon Carbide (SiC) based devices are identified as potential candidates for the mentioned application, featuring several improved characteristics over EMRs. On the contrary, other solutions, which seemed to be very promising, resulted to suffer from anomalous behaviors; i.e. SJ MOSFETs are thoroughly analysed by electro‐thermal physical simulations at the device level. Additionally, the Short Circuit (SC) capability of power semiconductor devices employed or with potential to be used in IH appliances is also analysed. On the one hand, conventional IGBTs SC behavior is evaluated under different test conditions so that to obtain the trade‐off between ruggedness and low power losses. Moreover, ruggedness and reliability of several normally‐off 600‐650 V GaN HEMTs are deeply investigated by experimentation and physics‐based simulation. Finally, power losses calculation at die‐level is performed for resonant power converters by means of using Infrared Thermography (IRT). This method assists to determine, at the die‐level, the power losses and current distribution in IGBTs used in resonant soft‐switching power converters when functioning within or outside the Zero Voltage Switching (ZVS) condition. As a result, relevant information is obtained related to decreasing the power losses during commutation in the final application, and a thermal model is extracted for simulation purposes.<br /

A Double-Sided Stack Low-Inductance Wire-Bondless SiC Power Module with a Ceramic Interposer

The objective of this dissertation research is to develop a novel three-dimensional (3-D) wire bondless power module package for silicon carbide (SiC) power devices to achieve a low parasitic inductance and an improved thermal performance. A half-bridge module consisting of 900-V SiC MOSFETs is realized to minimize stray parasitic inductance as well as to provide both vertical and horizontal cooling paths to maximize heat dissipation. The proposed 3-D power module package was designed, simulated, fabricated and tested. In this module, low temperature co-fired ceramic (LTCC) substrate with vias is utilized as an interposer of which both top and bottom sides are used as die attachment surfaces, the SiC MOSFET bare dies are flip-chip attached on the LTCC interposer using nickel-plated copper balls, high horizontally thermal conductive material is integrated into the LTCC interposer to improve its thermal dissipation capability. Hence, the LTCC interposer provides both electrical and thermal routing and the nickel-plated copper balls replace bond wires in conventional planar power module as the electrical interconnections for the SiC power devices. On the other side, direct bond copper (DBC) substrate are used at both top and bottom sides of the 3-D module to achieve electrical path for SiC devices and double-sided cooling. As a result, 3D power routing is achieved to reduce stray inductance, and both vertical and lateral paths are utilized to spread heat generated by the power devices in this compact module architecture. Electrical simulation was performed to extract the parasitic inductances in the 3-D package and compared to other reported module packages. Low loop parasitic inductance of 4.5nH at a frequency of 1MHz is achieved after optimization. Thermal and thermo-mechanical simulations were also conducted to evaluate the thermal performance and mechanical stress of the proposed module structure. The fabrication process flow of the 3-D wire bondless module is developed and presented. The fabricated half-bridge module was evaluated experimentally by double-pulse test and thermal cycling test. Significant reduction in voltage overshoot and ringing was observed during the double-pulse test, and the module shows no degradation after thermal cycling test. To push the double-sided wire-bondless module to higher voltage application, a 3.3-kV SiC double-sided wire-bondless common source module was designed, fabricated, and tested. Electric field simulations were performed considering the associated challenge of increased electric field strength in the higher-voltage wire-bondless module. High voltage blocking test was added to evaluate the high voltage operation capability as well

BUCK-BOOST DC-DC CONVERTER with INPUT PROTECTION SYSTEM FOR THE ENERGY HARVESTING from EXERCISE MACHINES PROJECT

Cal Poly’s Energy Harvesting from Exercise Machines (EHFEM) project comprises of multiple subprojects seeking to effectively create a sustainable energy source through harvesting electrical energy generated from physical exercise machines. This project designs and implements a Buck-Boost DC-DC converter using a LT3791-1 4-Switch Buck-Boost Controller, replacing the previous SEPIC design. The DC-DC converter must operate within limits set by the maximum input range of the LT3791-1 controller. An input protection system prevents inputs higher than rated values, which may adversely damage the Buck-Boost DC-DC converter. These inputs include overvoltage transients, average voltage, and current output by the Precor EFX 561i elliptical generator. Therefore, integrating a modified version of Ryan Turner and Zack Weiler’s DC-DC Converter Input Protection System prevents system damage if generator outputs stray beyond safe operational range. This system also provides charge accumulation protection generated during an open-load phase during start-up of the Enphase M175 Micro- Inverter. Additionally, the DC-DC converter’s output must provide a voltage within the micro-inverter’s input voltage range to apply 240VRMS power back to the electrical grid

Methods and Results of Power Cycling Tests for Semiconductor Power Devices

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 25