VLSI Implementation of Discrete Cosine Transform Based on the Shared-Multiplier Algorithm

In this paper a new algorithm for discrete cosine transform (DCT) is proposed. This algorithm is especially efficient for VLSI implementation because each multiplier in @e 1-D DCT is shared by two constants rather than one. This greatly reduces the chip area, and the high speed characteristics are still retained. Based on this algorithm, we have developed the corresponding bit-parallel, fully-pipelined architecture for the size-8 DCT. The core area of the chip is only 8.6mm x 8.5mm, using 1.2um double-metal single-poly CMOS technology. This chip is simulated for operation at the maximum speed of 100 MHz which far exceeds the speed requirement of the HDTV system (70 MHz)

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping," in

Abstract partition tends to produce better results. However, to the best of our knowledge, finding a good input partition in Roth-Karp decomposition has not been formally addressed in previous research. In this paper, we propose a new heuristics to solve this problem. Roth-Karp decomposition is a classical decomposition method. Because it can reduce the number of input variables of a function, it becomes one of the most popular techniques used in LUT-based FPGA technology mapping. However, the lambda set selection problem, which can dramatically affect the decomposition quality in Roth-Karp decomposition, has not been formally addressed before. In this paper, we propose a new heuristic-based algorithm to solve this problem. The experimental results show that our algorithm can efficiently produce outputs with better decomposition quality than that produced by other algorithms without using lambda set selection strategy

Inductance modeling for onchip interconnects

Abstract. As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization

The design of an LSI Booth multiplier : nMOS vs. CMOS technology

Computer Science Departmen

Compatible class encoding in Roth–Karp decomposition for two-output LUT architecture

The algorithm proposed in [11] provides a heuristic to choose a good lambda set. Another algorithm proposed in [10] formulates Problem 2 as a symbolic-input encoding problem. However, both of these two algorithms only consider the singleoutput LUT architecture. In this paper, we propose a new formulation for Problem 2 and develop a new compatible class encoding algorithm which can fully exploit the feature of the two-output LUT architecture. This paper is organized as follows. Section 2 describes the compatible class encoding problem in Roth-Karp decomposition. In Section 3, our new encoding algorithm which addresses the two-output LUT architecture is given in detail. Section 4 shows experimental results and the concluding remarks are given in Section 5

A power modeling and characterization method for macrocells using structure information

To characterize a macrocell, a general method is to store the power consumption of all possible transition events at primary inputs in the lookup tables. Though this approach is very accurate, the lookup tables could be huge for the macrocells with many inputs. In this paper, we present a new power modeling method which takes advantage of the structure information of macrocells and selects minimum number of primary inputs or internal nodes in a macrocell as state variables to build a state transition graph (STG). Those state variables can completely model the transitions of all internal nodes and the primary outputs. By carefully deleting some state variables, we further introduce an incomplete power modeling technique which can simplify the STG without losing much accuracy. In addition, we exploit the property of the compatible patterns of a macrocell to further reduce the number of edges in the corresponding STG. Experimental results show that our modeling techniques can provide SPICE-like accuracy and can reduce the size of the lookup table significantly comparing to the general approach. 1

Physical-based model of ink diffusion in Chinese paintings

Chinese ink painting is a traditional art that is over three thousand years old. It is a type of non-photorealistic rendering. However, research on Chinese ink painting is scarce. Simulating the behavior of Chinese ink is challenging work because ink moves in a complex manner. This paper presents a new method for simulating ink diffusion based on observation and analysis. The proposed method can simulate various expressions of tones on different types of paper. The elucidation of the effect of mixing simulated strokes made by different kinds of brushes is an important contribution of the method. Finally, the simulated results are compared with real ink painting