FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

Modular Multi-level Converter Hardware-in-the-Loop Simulation on low-cost System-on-Chip devices

Comunicació presentada a IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society (October 21-23, 2018 Washington D.C., USA.)System-on-Chip (SoC) devices combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for Hardware-in-the-Loop (HIL) simulation. One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which need extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ and SystemC. This paper evaluates SoC devices to implement a Modular Multi-Level Converter (MMC) model using HLS tools for being implemented in the FPGA fabric in order to perform HIL verification of control algorithms in a single low-cost device

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Industrial applications of the Kalman filter:a review

International audienc

SOM neural network design – a new Simulink library based approach targeting FPGA implementation

The paper presents a method for FPGA implementation of Self-Organizing Map (SOM) artificial neural networks with on-chip learning algorithm. The method aims to build up a specific neural network using generic blocks designed in the MathWorks Simulink environment. The main characteristics of this original solution are: on-chip learning algorithm implementation, high reconfiguration capability and operation under real time constraints. An extended analysis has been carried out on the hardware resources used to implement the whole SOM network, as well as each individual component block

Représentations Systèmes Multi-Machines (SMM) de machines polyphasées

Cet article présente le principe de décomposition de machines polyphasées en machines fictives monophasée et diphasées non couplées magnétiquement. Après la description de la méthodologie de décomposition SMM (Systèmes Multimachines Multiconvertisseurs), deux cas sont étudiés. Une machine synchrone pentaphasée, est d'abord analysée avec son modèle de machines équivalentes. Un second cas plus original est ensuite étudié : deux machines pentaphasées connectées en série et alimentées par un onduleur 5 bras.This paper presents the equivalence of multi-phase machines with a set a of 1-phase and 2-phase machines with no magnetic couplings. Two cases are then studied. First, a 5-phase machine supplied by a Voltage Source Inverter(VSI) is analyzed. Then, a model is established for a single 5-leg VSI supplying two 5-phase machines whose windings are connected in series

Analiza FPGA implementacije bilateralnih algoritama upravljanja za dodirnu teleoperaciju

This paper presents the FPGA implementation of sliding mode control algorithm for bilateral teleoperation, such that, the problem of haptic teleoperation is addressed. The presented study improves haptic fidelity by widening the control bandwidth. For wide control bandwidth, short control periods as well as short sampling periods are required that was achieved by the FPGA. The presented FPGA design methodology applies basic optimization methods in order to meet the required control period as well as the required hardware resource consumption. The circuit specification was performed by the high-level programing language LabVIEW using the fixed-point data type. Hence, short design times for producing the FPGA logic circuit can be achieved. The proposed FPGA-based bilateral teleoperation was validated by master-slave experimental device.Ovaj rad opisuje FPGA implementaciju algoritama upravljanja kliznim režimima za bilateralnu teleoperaciju, pri čemu je opisan problem haptičke teleoperacije. Prikazano istraživanje poboljšava dodirnu pouzdanost proširenjem upravljačkog propusnog pojasa. Za široki propusni pojas, potrebni su kratki upravljački periodi i brzo vrijeme uzorkovanja, što je postignuto primjenom FPGA sklopovlja. Prikazana metodologija za projektiranje FPGA sklopovlja koristi osnovne optimizacijske metode s ciljem postizanja potrebnih upravljačkih perioda i zahtijevane fizičke iskorištenosti sklopovlja. Specifikacije sklopovlja su provedene programskim jezikom visoke razine LabVIEW uz korištenje podataka s nepomičnim decimalnim zarezom. Stoga je moguće implementirati traženu logiku na FPGA sklopovlje u kratkom vremenu. Opisana bilateralna teleoperacija temeljena na FPGA slopovlju je testirana na eksperimentalnom postavu s nadre.enim i podre.enim čvorom

FPGA-based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery

Collision detection, which refers to the computational problem of finding the relative placement or con-figuration of two or more objects, is an essential component of many applications in computer graphics and robotics. In image-guided robotic surgery, real-time collision detection is critical for preserving healthy anatomical structures during the surgical procedure. However, the computational complexity of the problem usually results in algorithms that operate at low speed. In this paper, we present a fast and accurate algorithm for collision detection between Oriented-Bounding-Boxes (OBBs) that is suitable for real-time implementation. Our proposed Sweep and Prune algorithm can perform a preliminary filtering to reduce the number of objects that need to be tested by the classical Separating Axis Test algorithm, while the OBB pairs of interest are preserved. These OBB pairs are re-checked by the Separating Axis Test algorithm to obtain accurate overlapping status between them. To accelerate the execution, our Sweep and Prune algorithm is tailor-made for the proposed method. Meanwhile, a high performance scalable hardware architecture is proposed by analyzing the intrinsic parallelism of our algorithm, and is implemented on FPGA platform. Results show that our hardware design on the FPGA platform can achieve around 8X higher running speed than the software design on a CPU platform. As a result, the proposed algorithm can achieve a collision frame rate of 1 KHz, and fulfill the requirement for the medical surgery scenario of Robot Assisted Laparoscopy.published_or_final_versio

RÉFLEXIONS SUR LA MATÉRIALITÉ

International audienceRecueil de réflexions sur la matérialité en architecture