The ThomX project status

Work supported by the French Agence Nationale de la recherche as part of the program EQUIPEX under reference ANR-10-EQPX-51, the Ile de France region, CNRS-IN2P3 and Université Paris Sud XI - http://accelconf.web.cern.ch/AccelConf/IPAC2014/papers/wepro052.pdfA collaboration of seven research institutes and an industry has been set up for the ThomX project, a compact Compton Backscattering Source (CBS) based in Orsay - France. After a period of study and definition of the machine performance, a full description of all the systems has been provided. The infrastructure work has been started and the main systems are in the call for tender phase. In this paper we will illustrate the definitive machine parameters and components characteristics. We will also update the results of the different technical and experimental activities on optical resonators, RF power supplies and on the electron gun

Planck pre-launch status : The Planck mission

Peer reviewe

Firmware pour une carte de filtrage numérique faible latence

International audienceLe but de cette communication est de montrer au travers d’une application les possibilités d’un FPGA évolué, les critères qui vont rentrer en jeu pour le choix du FPGA, ainsi que les difficultés rencontrées pour se servir du potentiel de ce dernier. L’exposé commence par une présentation rapide de l’application dans laquelle s’insère lacarte-mère ainsi que du cahier des charges demandé. Je poursuis par une présentation du synoptique de la carte et des composants employés. Puis je développe plus largement tout ce qui ce rapporte au Fpga (constructeur Altera, famille Arria V), à savoir : •Critères pour choisir le FPGA. •Problèmes liés au pin-out.•Quelques Aspects de l’écriture du firmware en VHDl.•Certainesdifficultés liées aux IPs. •Utilisation des contraintes de timing

PCI-Express Based High-Speed Readout for the Belle II DAQ Upgrade

International audienceBelle II is a new-generation B-factory experiment, dedicated to exploring new physics beyond the standard model of elementary particles in the flavor sector. Belle II started data-taking in April 2018, using a synchronous data acquisition (DAQ) system based on pipelined trigger flow control. The Belle II DAQ system is designed to handle a 30-kHz trigger rate with approximately 1% of dead time, under the assumption of a raw event size of 1 MB. The DAQ system is reliable, and the overall data-taking efficiency reached 84.2% during the run period of January 2020–June 2020. The current readout system cannot be operated in the terms of ten years from the viewpoint of DAQ maintainability; meanwhile, the readout system is obstructing high-speed data transmission. A solution involving a peripheral component interconnect (PCI)-express-based readout module with high data throughput of up to 100 Gb/s was adopted to upgrade the Belle II DAQ system. We particularly focused on the design of firmware and software based on this new generation of readout board, called PCIe40, with an Altera Arria 10 field-programmable gate array chip. The 48-Gb transceiver (GBT) serial links, PCI-express hard IP-based direct memory access (DMA) architecture, interface of timing and trigger distribution system, and slow control system were designed to integrate with the current Belle II DAQ system. This article describes the performances accomplished during the data readout and slow control tests conducted using a test bench and a demonstration performed using on-site front-end electronics, specifically involving Belle II TOP and KLM subdetectors

Firmware Development of the PCI-express-based High-Speed Readout Board in the Upgrade of the Belle II DAQ System

International audienceThe Belle II experiment with SuperKEKB accelerator has started beam collision in 2018. With a higher luminosity, the target of Belle II is to improve the measurement of rare B meson decays and to probe for new physics. The present DAQ system in Belle II is designed to operate under a maximum trigger rate of 30 kHz at expected peak luminosity, and its stability has been confirmed in the early phases of the operation so far. Considering the difficulty of maintenance and the limited performance of the current read-out system, Belle II DAQ group is preparing an upgrade by using PCI-express-based readout board (PCIe40) which is capable of a higher data throughput of 100 Gb/s. PCIe40 board is based on an Intel Arria 10 field-programmable gate array, which has 48 transceivers and PCI-express DMA architecture. The PCIe40 firmware for Belle II needs to have many functionalities, such as custom Belle2Link protocol to detector Front-End, interface to trigger and timing distribution system, data processing logic for first-level event building, and DMA implementation. This paper describes the development of each item and performance tests with various Belle II detectors’ Front-End electronics (FEE), as well as the plan of integrating the new readout system in the Belle II global DAQ system

Development and Performance of the Belle II DAQ Upgrade

International audienceBelle II is a new-generation B-factory experiment operating at the luminosity frontier, SuperKEKB collider, and started data-taking in April 2018. Belle~II uses a synchronous data acquisition (DAQ) system based on a pipelined trigger flow control. It is designed to handle 30 kHz trigger rate, under the assumption of a raw event size 1 MB. Because a larger event size and rate are foreseen depending on the future background conditions, and the difficult maintainability of the current readout system during the Belle II entire operation period is expected, we decided to upgrade the Belle II DAQ readout system with state-of-art technology. A PCI Express based new-generation of readout board (PCIe40), which was originally developed for the upgrade of LHCb and ALICE experiments, has been used for the upgrade of Belle II DAQ system. PCIe40 is able to connect to a maximum of 48 frontend electronics through multi-gigabit serial links. PCI Express hard IP-based direct memory access architecture, the newly designed timing and trigger distribution system and slow control system make the Belle II readout setup a compact system. Three out of seven sub-detectors of Belle II experiment have been operated with the upgraded DAQ system during physics data-taking, development and performance for remaining sub-detectors have been accomplished and checked with cosmic data-taking and stress DAQ test

Trigger Timing Interface for the Read-Out Upgrade of the Belle II DAQ

International audienceTo improve data throughput of the Belle II data acquisition we are upgrading the CPU-based COPPER system with a PCIe40 board carrying Arria 10 FPGA. Since one of the main functionalities of the new system is event building in FPGA, the read-out system must be synchronized with the front-end electronics. This task is performed by the bidirectional trigger timing distribution system. During system commissioning, we prepared several versions of the interface to this system. In the initial version of the interface, we ported the code from Xilinx FPGAs to Arria 10. This revision also introduces monitoring of the status for multiple channels and a ring buffer to distribute trigger information to all channels in parallel. To improve stability under external noise, we implemented a clock-data recovery using an independent on-board oscillator as a reference clock in the next revision of the interface. We are also developing a version utilizing a high-speed serial transceiver to replace CAT-7 RJ45 cables with optical fibers. The system commissioning started in 2021 with a few detectors and will be completed after the long shutdown 1 of SuperKEKB in 2023. In this paper, we present the architectures of the interface to the trigger timing system implemented in the PCIe40 board and the system performance in the experiment