CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.2009 Asian Test Symposium, 23-26 November 2009, Taichung, Taiwa

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC\u2799 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.2011 Asian Test Symposium, 20-23 November 2011, New Delhi, Indi

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression

Capture safety has become a major concern in at-speed scan testing since strong power supply noise caused by excessive launch switching activity (LSA) at transition launching in an at-speed test cycle often results in severe timing-failure-induced yield loss. Recently, a basic RM (rescue-&-mask) test generation scheme was proposed for guaranteeing capture safety rather than merely reducing LSA to some extent. This paper extends the basic RM scheme to broadcast-scan-based test compression by uniquely solving two test-compression-induced problems, namely (1) input X-bit insufficiency (i.e., fewer input X-bits are available for LSA reduction due to test compression) and (2) output X-bit impact (i.e., output X-bits may reduce fault coverage due to test response compaction). This leads to the broadcast-RM (broadcast-scan-based rescue-&-mask) test generation scheme. Evaluations on large benchmark circuits and an industrial circuit of about 1M gates clearly demonstrate that this novel scheme can indeed guarantee capture safety in at-speed scan testing with broadcast-scan-based test compression while minimizing its impact on both test quality and test costs.2013 26th International Conference on VLSI Design, 5-10 January 2013, Pune, Indi

EFSA BIOHAZ Panel (EFSA Panel on Biological Hazards), 2013. Scientific Opinion on the public health hazards to be covered by inspection of meat (bovine animals).

A risk ranking process identified Salmonella spp. and pathogenic verocytotoxin-producing Escherichia coli (VTEC) as current high-priority biological hazards for meat inspection of bovine animals. As these hazards are not detected by traditional meat inspection, a meat safety assurance system for the farm-to-chilled carcass continuum using a risk-based approach was proposed. Key elements of the system are risk-categorisation of slaughter animals for high-priority biological hazards based on improved food chain information, as well as risk-categorisation of slaughterhouses according to their capability to control those hazards. Omission of palpation and incision during post-mortem inspection for animals subjected to routine slaughter may decrease spreading and cross-contamination with the high-priority biological hazards. For chemical hazards, dioxins and dioxin-like polychlorinated biphenyls were ranked as being of high potential concern; all other substances were ranked as of medium or lower concern. Monitoring programmes for chemical hazards should be more flexible and based on the risk of occurrence, taking into account the completeness and quality of the food chain information supplied and the ranking of chemical substances, which should be regularly updated to include new hazards. Control programmes across the food chain, national residue control programmes, feed control and monitoring of environmental contaminants should be better integrated. Meat inspection is a valuable tool for surveillance and monitoring of animal health and welfare conditions. Omission of palpation and incision would reduce detection effectiveness for bovine tuberculosis and would have a negative impact on the overall surveillance system especially in officially tuberculosis free countries. The detection effectiveness for bovine cysticercosis, already low with the current meat inspection system, would result in a further decrease, if palpation and incision are removed. Extended use of food chain information could compensate for some, but not all, the information on animal health and welfare lost if only visual post-mortem inspection is applied

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits

VTS : 2012 IEEE 30th VLSI Test Symposium , 23-25 Apr. 2012 , Maui, HI, USAExcessive capture power in at-speed scan testing may cause yield loss due to timing failures. Although reducing the number of clock domains that capture test responses simultaneously is a practical and scalable solution for reducing capture power, no available capture-safety checking metric can assess its effect in an accurate-enough manner, especially when multiple clock domains capture test responses in a short period of time. This paper proposes a novel CLEAR (CLock-Edge-Arrival-Relation-based) capture-safety checking method that, for the first time, takes clock edge arrival times for different clock domains into consideration. The accuracy and usefulness of the proposed method have been clearly demonstrated by simulation-based evaluation with the largest ITC'99 benchmark circuit as well as real-chip-based evaluation with an industrial chip embedded with on-chip delay measurement circuitry

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

ISLPED : 2011 International Symposium on Low Power Electronics and Design , 1-3 Aug 2011 , Fukuoka, JapanExcessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing