Dynamic Discrepancy Reduced Order Modeling for Fischer-Tropsch Synthesis Over Cobalt-based Catalyst

Advances in carbon capture techniques and demands in alternative fuel sources have increased over the past couple of decades. The Fischer-Tropsch Synthesis (FTS) provides a viable way to produce hydrocarbons from natural gas, coal, CO2, or biomass. However, current comprehensive models for FTS encompass large number of reacting species, readsorption and conversion of primary products, surface intermediates, and coverage-dependent reaction rates. To accurately predict the products obtained through the process a reduced order model has been developed. By reducing the number of parameters of an existing comprehensive model, uncertainty is introduced. The uncertainty can be quantified by using discrepancy functions within the chemical rate equations, there by representing the reduced order model as a set of stochastic differential equations. Representing the uncertainty as model discrepancy functions, a Bayesian approach is used to calibrate the reduced order model to data obtained from literature. Through a Bayesian Smoothing Splines (BSS-ANOVA) framework, the stochastic differential equations are decoupled into deterministic differential equations and stochastic coefficients. The parameters are solved for using a Sequential Monte Carlo approach with importance sampling. Through the use of these stochastic coefficients, fidelity is restored to the reduced order model. Thus, the model can be fully described by fewer parameters than initially needed, as well as a reduction in the computational complexity

Analyzing SMEs Size as a Moderator of ERP Impact in SMEs Productivity

Enterprise Resource Planning (ERP) vendors have emphasized a positive impact of their ERP projects in enterprise performance and in costs reduction. Recently, some researchers have started to analyze the impact on business performance of the organizational changes that complement IT investments. However, there is a lack of research studies on ERP impact in Small and Medium Enterprises (SME). Based on Cobb-Douglas production function, this paper attempts to analyze the impact of ERP implementations in SMEs’ productivity. We have collected data from 168 Spanish SMEs during the period 1997-2005, concerning the type of purchased ERP, implementation period, number of employees and some financial indicators. We use a cross-sectional and time-series model to compare and analyze the SMEs’ productivity evolution, before and after ERP implementations considering SMEs size as a critical variable to determine the level of productivity reached. Our preliminary findings suggest that SMEs size moderates ERP impact in their productivity. Therefore, researchers and practitioners should not consider all SMEs in the same package and they should have different strategies and approaches to obtain the best results in each ERP implementation

An Updated ERP Systems Annotated Bibliography: 2001-2005

The goal of this study is to provide an updated annotated bibliography of ERP publications published in the main IS conferences and journals during the period 2001-2005, categorizing them through an ERP lifecycle based framework that is structured in phases. The first version of this bibliography was published in 2001 (Esteves and Pastor, 2001c). However, so far, we have extended the bibliography with a significant number of new publications in all the categories used in this paper. We also reviewed the categories and some incongruities were eliminated. Furthermore, we present topics for further research in each phase

Overcoming Knowledge Integration Barriers in ERP Implementation Using Action Research Approach

This study focuses on documenting the barriers of knowledge integration between the organizational culture and the bestpractices supported by an ERP system using an Action Research approach. The findings contribute to the ERP literature because they provide managers with different knowledge integration barriers that appear during ERP implementation, and how authors, using an AR methodology, surpassed these problems. Moreover, this study offers a knowledge integration perspective to understand the ERP implementation as a whole process that involves internal and external stakeholders. In this regard, the training with a holistic vision is suggested to increase the likelihood of success of the ERP implementation project. Finally, some trends for future research are provided

A 0.6V 2.9µW mixed-signal front-end for ECG monitoring

This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V[subscript T] digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.Texas Instruments IncorporatedNatural Sciences and Engineering Research Council of Canada (Fellowship

Digitally-assisted, ultra-low power circuits and systems for medical applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 219-225).In recent years, trends in the medical industry have created a growing demand for a variety of implantable medical devices. At the same time, advances in integrated circuits techniques, particularly in CMOS, have opened possibilities for advanced implantable systems that are very small and consume minimal energy. Minimizing the volume of medical implants is important as it allows for less invasive procedures and greater comfort to patients. Minimizing energy consumption is imperative as batteries must last at least a decade without replacement. Two primary functions that consume energy in medical implants are sensor interfaces that collect information from biomedical signals, and radios that allow the implant to communicate with a base-station outside of the body. The general focus of this work was the development of circuits and systems that minimize the size and energy required to carry out these two functions. The first part of this work focuses on laying down the theoretical framework for an ultra-low power radio, including advances to the literature in the area of super-regeneration. The second part includes the design of a transceiver optimized for medical implants, and its implementation in a CMOS process. The final part describes the design of a sensor interface that leverages novel analog and digital techniques to reduce the system's size and improve its functionality. This final part was developed in conjunction with Marcus Yip.by Jose L. Bohorquez.Ph.D

Diseño de una red adsl de servicios de banda ancha para la urbanización samanes con acceso a internet a través del cable panamericano

En este artículo se hace una descripción de las tecnologías xDSL, ADSL y el protocolo ATM. También se presentará el concepto y las especificaciones del Cable Panamericano y una pequeña reseña de los proveedores de Internet que están conectados al cable Panamericano. También se presenta el estado actual de los servicios de banda ancha en el Ecuador, así como de la problemática existente en la ciudad de Guayaquil, debido a la falta de proveedores de banda ancha a bajo costo, presentando la tecnología ADSL como solución al problema. Se hace mayor énfasis en los servicios de Internet y transmisión datos de banda ancha. Se hace el planteamiento y diseño del proyecto de una red ADSL en una urbanización. También se presenta la descripción del enlace dedicado al Cable Panamericano y todas sus consideraciones técnicas, así como del proveedor de Internet en el exterior. Finalmente, se analizan las ventajas y desventajas técnicas, económicas, así como consideraciones sociales y legales

Diseño de propuesta de actualización tecnológica para control y supervisión en planta de producción Los Toros del municipio de Trinidad, Casanare.

NingunoEl presente trabajo pretende dar a conocer la manera de migrar o actualizar un sistema de control para una planta de producción. Se enfoca en la contextualización de la tecnología existente la cual se desarrolla con controladores y su comunicación se establece por protocolo modbus. Mediante la propuesta se tendrá un sistema de control distribuido con supervisorio integrado por PLC siemens y gestionado en una red de comunicación Profinet/Industrial Ethernet. En el desarrollo de este documento se analizan los recursos necesarios para la implementación y las consideraciones que se deben tener en cuenta en su aplicación en la automatización del proceso. Finalmente, y con el software de Siemens TIA PORTAL (Totally Integrated Automation) que integra programación y diseño se realizan pruebas de simuladas donde verificaremos el funcionamiento y la correcta implementación de la propuesta a partir de la lógica de campo para la estación Los Toros ubicada en el municipio de Trinidad en Casanare y operada por la empresa PERENCO.This work aims to show how to migrate or update a control system for a production plant. It focuses on the contextualization of existing technology, which is developed with controllers and its communication is established by modbus protocol. Through the proposal there will be a distributed control system with supervision integrated by Siemens PLC and managed in a Profinet / Industrial Ethernet communication network. In the development of this document, the resources necessary for the implementation and the considerations that must be taken into account in their application in the automation of the process are analyzed. Finally, and with the Siemens TIA PORTAL (Totally Integrated Automation) software that integrates programming and design, simulated tests are carried out where we will verify the operation and correct implementation of the proposal from the field logic for the Los Toros station located in the municipality of Trinidad in Casanare and operated by the PERENCO company

Stress-Sensing-Chip for silicon integrated circuits and packaged electronic devices

Orientador: Fabiano FruettTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: A deformação da rede cristalográfica de um semicondutor gera variações em características elétricas importantes dos semicondutores, incluindo a mobilidade de portadores, impactando, assim, as características e os parâmetros de operação dos circuitos integrados. A deformação é causada pelo estresse mecânico remanescente, o qual é induzido na fabricação e, principalmente, através do processo de empacotamento. Sensores que podem ser integrados na superfície dos dispositivos são uma excelente ferramenta para quantificação tanto do estresse gerado, quanto da relação deste com as variáveis presentes no processo de empacotamento. Um tal processo possibilita identificar pontos críticos e reduzir o estresse, aumentando a produtividade final. Apresentamos neste trabalho uma série de piezo-transdutores octogonais baseados no efeito piezo-resitivo do silício, fabricados usando uma tecnologia CMOS comercial (XFABc06 ), que foram projetados para identificar os principais componentes do estresse mecânico paralelo à superfície ativa de circuitos integrados de silício. Como os dispositivos são totalmente compatíveis com a tecnologia CMOS, são excelentes ferramentas para identificar e mapear o estresse de forma não invasiva. Todo o projeto dos sensores foi baseado no efeito piezo-resistivo do silício e sustentado tanto em simulações de circuitos elétricos, quanto em simulações multi-fisícas de modelos de elementos finitos (FEM), usando ferramentas computacionais de projeto, como CADENCE Virtuoso® e COMSOL Multyphysic®. O primeiro modelo de sensor de estresse apresentado integra piezo-resistores com 4 orientações diferentes, em um único dispositivo octogonal, sendo denominado como sensor piezo-resistor de oito terminais (8TSP - Eight Terminal Silicon Piezotransducer). O sensor foi fabricado usando as mesmas camadas requeridas para um resistor de difusão tipo-n, e apresenta uma resposta em tensão bastante linear com o estresse. Ao polarizarmos o dispositivo em diferentes orientações foi possível estimar a orientação e magnitude do estresse uniaxial. Fontes de referência, multiplexadores analógicos e um circuito para compensar a deriva térmica foram implementados para construir uma solução completa para mapear o estresse. Um CHIP de teste de estresse com 32 destes dispositivos foi fabricado e usado para determinar o estresse em uma montagem de teste. Com os resultados da caracterização do primeiro protótipo, desenvolvemos uma segunda geração, substituindo os resistores por transistores piezoMOS. A fim de projetar um sensor de estresse mais compacto e com um consumo menor, integramos espelhos de corrente onde os transistores foram posicionados, obedecendo à diferentes orientações. Dois modelos foram fabricados usando transistores PMOS e NMOS. Os sensores apresentaram uma saída em corrente, a qual se mostrou menos susceptível ao ruído, podendo ser facilmente operada usando espelhos de corrente. Fontes de referência, portas de transmissão e um ADC de 1-bit foram integrados para construir uma solução completa. Um CHIP de teste de estresse com 64 destes dispositivos foi fabricado e usado para determinar o estresse em uma montagem de testeAbstract: Strain in the crystal lattice of a semiconductor material generates a drift in important electrical characteristics of the semiconductors, including the mobility of carriers and intrinsic carrier concentration, which also impacts the characteristics and operating parameters of the integrated circuits (ICs). This deformation is caused by the remaining mechanical stress, a random stress that is induced by fabrication process and, mainly, by the electronic packaging. In order to detect stress-related problems, sensors that can be integrated in the surface of the devices are an excellent tool to quantify the stress generated and its relation with the variables present in the packaging process, which allows to identify critical points and reduce stress, thus increasing the final yield and reliability of the devices. A series of piezo-transducers based on the piezo-resistive effect of silicon are introduced in this work, those devices were manufactured using commercial CMOS technology (XFABc06 ), and they are specially designed to study the main components of the in-plane mechanical stress along the active surface of silicon ICs. Because the devices are fully compatible with CMOS technology, they are non-invasive tools for identifying and mapping stress. The designs are based on the mathematical model of piezo-resistive effect in silicon and they are supported on electrical circuit simulations and multi-physics finite element models simulations using computational design tools such as CADENCE Virtuoso® and COMSOL Multyphysic®. The first stress sensor presented integrates piezo-resistors with 4 different orientations into a single octagonal device, so it is denominated as 8TSP - Eight Terminal Silicon Piezotransducer. The sensor was fabricated using the same layers required for a n-type diffusion resistor, and presents a fairly linear stress response. It was possible to estimate the orientation and magnitude of the uniaxial stress with a single device biased different orientations. A BandGap Reference generator, analog multiplexers and a circuit to compensate for thermal drift were integrated with the sensor to deliver a complete solution. A Stress-test CHIP with 32 of these devices was manufactured and used to map the stress along the CHIP. With the results from the characterization of the first prototype, we developed a second generation of the stress sensor, replacing the resistors by piezoMOS transistors. We integrate current mirrors, in which the transistors are positioned with different orientations to design a sensor of stress more compact and with a lower power consumption. Two models were fabricated using PMOS and NMOS transistors. The sensors have a current output, which is less susceptible to noise and can be easily operated using current mirrors. Reference current generator, current mirrors, transmission gates and a 1-bit ADC were integrated to build a complete solution. A CHIP stress test with 64 of these devices was manufactured and used to determine stress in a test setDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutor em Engenharia Elétric

Factores asociados a la deserción escolar en la institución educativa centro de comercio de piedecuesta.

Figura 1. Matrícula total por nivel educativo y sector 2002-2012 (Número de Estudiantes) Figura 2. Tasa de Permanencia por Zona Fuente: E. ESPÍNDOLA, A. y LEÓN, A. (2002) La deserción escolar en América Latina: Un tema prioritario para la Agenda Nacional. REVISTA IBEROAMERICANA DE EDUCACIÓN. Nº 30Proyecto de Investigación de tipo descriptivo, realizado en el EDUCATIVA CENTRO DE COMERCIO DE PIEDECUESTA (CEDECO), institución educativa pública, dirigido a identificar los diferentes factores que inciden en la deserción escolar en la misma, mediante recolección de información a través de encuestas estructuradas y semiestructuradas, y otras fuentes secundarias.Research project of a descriptive type, carried out in the EDUCATIONAL CENTER OF COMMERCE OF PIEDECUESTA (CEDECO), a public educational institution, aimed at identifying the different factors that affect school dropout in it, by collecting information through structured surveys and semi-structured, and other secondary sources