STUDIES ON THE SYNTHESIS OF SOME NEW 1,2,4- TRIAZOLES DERIVATIVES AND EVALUATION FOR THEIR ANTI-FUNGAL ACTIVITY PROFILES

The synthesis of new heterocyclic compounds has always drawn the attention of medicinal chemist over the years mainly because they possess diverse biological properties. The literature survey on 1,2,4-triazoles revealed that they are endowed with wide variety of biological activities .During the present investigation a series of new 1,2,4-triazole derivatives N-(3-(2-(3- hydrazinyl-3-oxoalkanoyl)hydrazinyl)-5-(phenoxymethyl)-4H-1,2,4-triazol-4-yl)isonicotinamide(6a- 6e)were synthesized by reacting withN-(5-mercapto-3-(phenoxymethyl)-4H-1,2,4-triazol-4- yl)isonicotinamide (5) and aliphatic dicarboxylic acid hydrazides (a-e). The structures of the newly All the compounds synthesised 6a to 6e were evaluated for antifungal activity against Candida albicans and Aspergillus Niger was carried out and MIC values were determined synthesized compounds were estblished by FT-IR, 1H-NMR and MASS spectral analysis. The compound 6a (n=0) was found to be the most potent antifungal agent. Keywords: 1,2,4-triazole derivatives, antifungal, Candida albicans, Aspergillus Nige

Current mode fractional order filters using VDTAs with Grounded capacitors

In this work, the design of current mode Fractional order filter using VDTAs (Voltage differencing trans-conductance amplifier) as an active element with grounded capacitors has been proposed. The approximate transfer functions of low and high pass filters of fractional order on the basis of the integer order transfer has been shown and the form of those functions of filters is also implemented using VDTA as an active building block. In this work, filters of the different sequence have been realized. The frequency domain simulation results of the proposed filters are obtained on Matlab and PSPICE with TSMC CMOS 180 nm technology parameters. Stability and sensitivity is also verifie

Low Leakage and Robust Sub-threshold SRAM Cell using Memristor

This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared

Low Leakage and Robust Sub-threshold SRAM Cell using Memristor

This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared

Design and analysis of SOI and SELBOX junctionless FinFET at sub-15 nm technology node

969-975The structural and operational characteristics of a silicon on insulator (SOI) junctionless (JL) FinFET have been compared with the selective buried oxide (SELBOX) JL FinFET for 15 nm gate length and beyond using simulation studies. Simulations have been performed using silvaco TCAD (Atlas 3-D Module). SELBOX JL FinFET device has shown ~10 times improvement in ION/IOFF ratio with respect to the SOI JL FinFET. The SELBOX based device has subthreshold slope (SS) value of 69.08 mV/Dec whereas this is 84.1 mV/Dec for SOI based device. SELBOX JL FinFET has DIBL value of 31.57 mV/V whereas this is 119 mV/V for SOI JL FinFET. The comparison results, discussed, are for the channel length (gate length) of 15 nm. Furthermore, short-channel characteristics for the n-channel and p-channel SELBOX JL FinFET have been discussed. For channel length of 5 nm (which is a future technology node for mass production of semiconductor devices and systems), SELBOX device has shown favourable value of ION/IOFF ratio as 106 and SS as 96.86 mV/Dec. SELBOX JL FinFET has shown more immunity towards self-heating effect compared to the SOI JL FinFET. Performance of the SELBOX JL FinFET can be enhanced further independently by tuning various parameters such as the buried oxide thickness, the gap between buried oxide layers, substrate doping, and substrate bias

Design and analysis of SOI and SELBOX junctionless FinFET at sub-15 nm technology node

The structural and operational characteristics of a silicon on insulator (SOI) junctionless (JL) FinFET have been compared with the selective buried oxide (SELBOX) JL FinFET for 15 nm gate length and beyond using simulation studies. Simulations have been performed using silvaco TCAD (Atlas 3-D Module). SELBOX JL FinFET device has shown ~10 times improvement in ION/IOFF ratio with respect to the SOI JL FinFET. The SELBOX based device has subthreshold slope (SS) value of 69.08 mV/Dec whereas this is 84.1 mV/Dec for SOI based device. SELBOX JL FinFET has DIBL value of 31.57 mV/V whereas this is 119 mV/V for SOI JL FinFET. The comparison results, discussed, are for the channel length (gate length) of 15 nm. Furthermore, short-channel characteristics for the n-channel and p-channel SELBOX JL FinFET have been discussed. For channel length of 5 nm (which is a future technology node for mass production of semiconductor devices and systems), SELBOX device has shown favourable value of ION/IOFF ratio as 106 and SS as 96.86 mV/Dec. SELBOX JL FinFET has shown more immunity towards self-heating effect compared to the SOI JL FinFET. Performance of the SELBOX JL FinFET can be enhanced further independently by tuning various parameters such as the buried oxide thickness, the gap between buried oxide layers, substrate doping, and substrate bias

Low Power Non-Volatile 7T1M Subthreshold SRAM Cell

A new modified 7T1M non-volatile SRAM cell is presented in this paper for low power applications at subthresholdvoltage (very low voltage) simply by connecting the memristor directly with storage node which is acting as storage elementand adding a transistor in between the two storage nodes with feedback connection gives better performance in terms ofaverage delay, read /write operations and RSNM/WSNM. The memristor based circuits are simulated at subthreshold is anew insight and a new effort in technology made with improvement of approximately 61% and 23% of RSNM and WSNMrespectively compared to existing memory cell 7T1M and power dissipation is decreased by 66% whereas read delay andwrite delay obtained is nominal. Moreover, It has also simulated an adjusting 6T2M and conventional 6T at subthresholdvoltage i.e. VDD=0.3V to compare its stability behaviour at lower supply voltage

Spin dephasing in Silicon Germanium nanowires

We study spin polarized transport in silicon germanium nanowires using a semiclassical monte carlo approach. Spin depolarization in the channel is caused due to D'yakonov-Perel (DP) relaxation associated with Rashba spin orbit coupling and due to Elliott- Yafet (EY) relaxation. We investigate the dependence of spin dephasing on germanium mole fraction in silicon germanium nanowires. The spin dephasing lengths decrease with an increase in the germanium mole fraction. We also find that the temperature has a strong influence on the dephasing rate and spin relaxation lengths increase with decrease in temperature. The ensemble averaged spin components and the steady state distribution of spin components vary with initial polarization.Comment: 17 pages, 10 figures include

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

387-394Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node

Measurement of t(t)over-bar normalised multi-differential cross sections in pp collisions at root s=13 TeV, and simultaneous determination of the strong coupling strength, top quark pole mass, and parton distribution functions

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