Copper Electrodeposition in Mesoscale Through-Silicon-Vias

Copper (Cu) electrodeposition (ECD) in through-silicon-vias (TSVs) is an essential technique required for high-density 3-D integration of complex semiconductor devices. The importance of Cu ECD in damascene interconnects has led to a natural development towards copper electrodeposition in TSVs. Cu ECD is preferred over alternative approaches like the chemical vapor deposition (CVD) of tungsten (W) or aluminum (Al) because Cu ECD films have lower film stress, lower processing temperatures, and more optimal thermal and electrical properties as compared with CVD W or Al. Via filling with electroplated Cu on substrates that have undergone atomic layer deposition of a conformal platinum seed metal is investigated herein. These mesoscale vias (600 μm depth, 5:1 aspect ratio) will be utilized in ultra-high-vacuum systems and thus require a uniform, void-free Cu deposit of sufficient thickness to prevent device degradation due to skin effects when RF frequencies as high as 100 V at 100 MHz are used. Conformally Cu-lined TSVs are achieved through the implementation of a complex ECD parameter scheme, and these results are compared with computational finite element modeling (FEM) outcomes. A novel, single additive chemistry is also developed and implemented to achieve fully filled void-free mesoscale TSVs within 6 hours of plating time, which represents an extraordinarily fast and controllable plating rate (100 μm/hour) for interconnect (IC) feature filling

Chemical Vapor Deposition of Thin Film Materials for Copper Interconnects in Microelectronics

The packing density of microelectronic devices has increased exponentially over the past four decades. Continuous enhancements in device performance and functionality have been achieved by the introduction of new materials and fabrication techniques. This thesis summarizes the thin film materials and metallization processes by chemical vapor deposition (CVD) developed during my graduate study with Professor Gordon at Harvard University. These materials and processes have the potential to build future generations of microelectronic devices with higher speeds and longer lifetimes. Manganese Silicate Diffusion Barrier: Highly conformal, amorphous and insulating manganese silicate $(MnSi_xO_y)$ layers are formed along the walls of trenches in interconnects by CVD using a manganese amidinate precursor vapor that reacts with the surfaces of the insulators. These $(MnSi_xO_y)$ layers are excellent barriers to diffusion of copper, oxygen and water. Manganese Capping Layer: A selective CVD manganese capping process strengthens the interface between copper and dielectric insulators to improve the electromigration reliability of the interconnects. High selectivity is achieved by deactivating the insulator surfaces using vapors containing reactive methylsilyl groups. Manganese at the Cu/insulator interface greatly increases the strength of adhesion between the copper and the insulator. Bottom-up Filling of Copper and Alloy in Narrow Features: Narrow trenches, with widths narrow than 30 nm and aspect ratios up to 9:1, can be filled with copper or copper-manganese alloy in a bottom-up fashion using a surfactant-catalyzed CVD process. A conformal manganese nitride $(Mn_4N)$ layer serves as a diffusion barrier and adhesion layer. Iodine atoms chemisorb on the $Mn_4N$ layer and are then released to act as a catalytic surfactant on the surface of the growing copper layer to achieve void-free, bottom-up filling. Upon post-annealing, manganese in the alloy diffuses out from the copper and forms a self-aligned barrier in the surface of the insulator. Conformal Seed Layers for Plating Through-Silicon Vias: Through-silicon vias (TSV) will speed up interconnections between chips. Conformal, smooth and continuous seed layers in TSV holes with aspect ratios greater than 25:1 can be prepared using vapor deposition techniques. $Mn_4N$ is deposited conformally on the silica surface by CVD to provide strong adhesion at Cu/insulator interface. Conformal copper or Cu-Mn alloy seed layers are then deposited by an iodine-catalyzed direct-liquid-injection (DLI) CVD process.Chemistry and Chemical Biolog

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Three wafer stacking for 3D integration.

Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation

Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity