Analog Reconfigurable Circuits

The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA.

Timed array antenna system : application to wideband and ultra-wideband beamforming receivers

Antenna array systems have a broad range of applications in radio frequency (RF) and ultra-wideband (UWB) communications to receive/transmit electromagnetic waves from/to the sky. They can enhance the amplitude of the input signals, steer beams electronically, and reject interferences thanks to beamforming technique. In an antenna array beamforming system, delay cells with the tunable capability of delay amount compensate the relative delay of signals received by antennas. In fact, each antenna almost acts individually depending upon time delaying effects on the input signals. As a result, the delay cells are the basic elements of the beamforming systems. For this purpose, novel active true time delay (TTD) cells suitable for RF antenna arrays have been presented in this thesis. These active delay cells are based on 1st- and 2nd-order all-pass filters (APFs) and achieve quite a flat gain and delay within up to 10-GHz frequency range. Various techniques such as phase linearity and delay tunability have been accomplished to improve the design and performance. The 1st-order APF has been designed for a frequency range of 5 GHz, showing desirable frequency responses and linearity which is comparable with the state-of-the-art. This 1st-order APF is able to convert into a 2nd-order APF via adding a grounded capacitor. A compact 2nd-order APF using an active inductor has been also designed and simulated for frequencies up to 10 GHz. The active inductor has been utilized to tune the amount of delay and to reduce the on-chip size of the filter. In order to validate the performance of the delay cells, two UWB four-channel timed array beamforming receivers realized by the active TTD cells have been proposed. Each antenna channel exploits digitally controllable gain and delay on the input signal and demonstrates desirable gain and delay resolutions. The beamforming receivers have been designed for different UWB applications depending on their operating frequency ranges (that is, 3-5 and 3.1-10.6 GHz), and thus they have different system requirements and specifications. All the circuits and topologies presented in this dissertation have been designed in standard 180-nm CMOS technologies, featuring a unity gain frequency ( ft) up to 60 GHz.Els sistemes matricials d’antenes tenen una àmplia gamma d’aplicacions en radiofreqüència (RF) i comunicacions de banda ultraampla (UWB) per rebre i transmetre ones electromagnètics. Poden millorar l’amplitud dels senyals d’entrada rebuts, dirigir els feixos electrònicament i rebutjar les interferències gràcies a la tècnica de formació de feixos (beamforming). En un sistema beamforming de matriu d’antenes, les cèl·lules de retard amb capacitat ajustable del retard, compensen aquest retard relatiu dels senyals rebuts per les diferents antenes. De fet, cada antena gairebé actua individualment depenent dels efectes de retard de temps sobre el senyals d’entrada. Com a resultat, les cel·les de retard són els elements bàsics en el disseny dels actuals sistemes beamforming. Amb aquest propòsit, en aquesta tesi es presenten noves cèl·lules actives de retard en temps real (TTD, true time delay) adequades per a matrius d’antenes de RF. Aquestes cèl·lules de retard actives es basen en cèl·lules de primer i segon ordre passa-tot (APF), i aconsegueixen un guany i un retard força plans, en el rang de freqüència de fins a 10 GHz. Diverses tècniques com ara la linealitat de fase i la sintonització del retard s’han aconseguit per millorar el disseny i el rendiment. La cèl·lula APF de primer ordre s’ha dissenyat per a un rang de freqüències de fins a 5 GHz, mostrant unes respostes freqüencials i linealitat que són comparables amb l’estat de l’art actual. Aquestes cèl·lules APF de primer ordre es poden convertir en un APF de segon ordre afegint un condensador més connectat a massa. També s’ha dissenyat un APF compacte de segon ordre que utilitza una emulació d’inductor actiu per a freqüències de treball de fins a 10 GHz. S’ha utilitzat l'inductor actiu per ajustar la quantitat de retard introduït i reduir les dimensions del filtre al xip. Per validar les prestacions de les cel·les de retard propostes, s’han proposat dos receptors beamforming basats en matrius d’antenes de 4 canals, realitzats por cèl·lules TTD actives. Cada canal d’antena aprofita el guany i el retard controlables digitalment aplicats al senyal d’entrada, i demostra resolucions de guany i retard desitjables. Els receptors beamforming s’han dissenyat per a diferents aplicacions UWB segons els seus rangs de freqüències de funcionament (en aquest cas, 3-5 i 3,1-10,6 GHz) i, per tant, tenen diferents requisits i especificacions de disseny del sistema. Tots els circuits i topologies presentats en aquesta tesi s’han dissenyat en tecnologies CMOS estàndards de 180 nm, amb una freqüència de guany unitari (ft) de fins a 60 GHz.Postprint (published version

Design of broadband inductor-less RF front-ends with high dynamic range for G.hn

System-on-Chip (SoC) was adopted in recent years as one of the solutions to reduce the cost of integrated systems. When the SoC solution started to be used, the final product was actually more expensive due to lower yield. The developments in integrated technology through the years allowed the integration of more components in lesser area with a better yield. Thus, SoCs became a widely used solution to reduced the cost of the final product, integrating into a single-chip the main parts of a system: analog, digital and memory. As integrated technology kept scaling down to allow a higher density of transistors and thus providing more functionality with the same die area, the analog RF parts of the SoC became a bottleneck to cost reduction as inductors occupy a large die area and do not scale down with technology. Hence, the trend moves toward the research and design of inductor-less SoCs that further reduce the cost of the final solution. Also, as the demand for home networking high-data-rates communication systems has increased over the last decade, several standards have been developed to satisfy the requirements of each application, the most popular being wireless local area networks (WLANs) based on the IEEE 802.11 standard. However, poor signal propagation across walls make WLANs unsuitable for high-speed applications such as high-definition in-home video streaming, leading to the development of wired technologies using the existing in-home infrastructure. The ITU-T G.hn recommendation (G.9960 and G.9961) unifies the most widely used wired infrastructures at home (coaxial cables, phone lines and power lines) into a single standard for high-speed data transmission of up to 1 Gb/s. The G.hn recommendation defines a unified networking over power lines, phone lines and coaxial cables with different plans for baseband and RF. The RF-coax bandplan, where this thesis is focused, uses 50 MHz and 100 MHz bandwidth channels with 256 and 512 carriers respectively. The center frequency can range from 350 MHz to 2450 MHz. The recommendation specifies a transmission power limit of 5 dBm for the 50 MHz bandplan and 8~dBm for the 100 MHz bandplan, therefore the maximum transmitted power in each carrier is the same for both bandplans. Due to the nature of an in-home wired environment, receivers that can handle both very large and very small amplitude signals are required; when transmitter and receiver are connected on the same electric outlet there is no channel attenuation and the signal-to-noise-plus-distortion ratio (SNDR) is dominated by the receiver linearity, whereas when transmitter and receiver are several rooms apart channel attenuation is high and the SNDR is dominated by the receiver noise figure. The high dynamic range specifications for these receivers require the use of configurable-gain topologies that can provide both high-linearity and low-noise for different configurations. Thus, this thesis has been aimed at researching high dynamic range broadband inductor-less topologies to be used as the RF front-end for a G.hn receiver complying with the provided specifications. A large part of the thesis has been focused on the design of the input amplifier of the front-end, which is the most critical stage as the noise figure and linearity of the input amplifier define the achievable overall specifications of the whole front-end. Three prototypes has been manufactured using a 65 nm CMOS process: two input RFPGAs and one front-end using the second RFPGA prototype.El "sistema en un chip" (SoC) fue adoptado recientemente como una de las soluciones para reducir el coste de sistemas integrados. Cuando se empezó a utilizar la solución SoC, el producto final era más caro debido al bajo rendimiento de producción. Los avances en tecnología integrada a lo largo de los años han permitido la integración de más componentes en menos área con mejoras en rendimiento. Por lo tanto, SoCs pasó a ser una solución ampliamente utilizada para reducir el coste del producto final, integrando en un único chip las principales partes de un sistema: analógica, digital y memoria. A medida que las tecnologías integradas se reducían en tamaño para permitir una mayor densisdad de transistores y proveer mayor funcionalidad con la misma área, las partes RF analógicas del SoC pasaron a ser la limitación en la reducción de costes ya que los inductores ocupan mucha área y no escalan con la tecnología. Por lo tanto, las tendencias en investigación se mueven hacia el diseño de SoCs sin inductores que todavía reducen más el coste final del producto. También, a medida que la demanda en sistemas de comunicación domésticos de alta velocidad ha crecido a lo largo de la última década, se han desarrollado varios estándares para satisfacer los requisitos de cada aplicación, siendo las redes sin hilos (WLANs) basadas en el estándar IEEE 802.11 las más populares. Sin embargo, una pobre propagación de señal a través de las paredes hacen que las WLANs sean inadecuadas para aplicaciones de alta-velocidad como transmisión de vídeo de alta definición en tiempo real, resultando en el desarrollo de tecnologías con hilos utilizando la infraestructura existente en los domicilios. La recomendación ITU-T G.hn (G.9960 and G.9961) unifica las principales infraestructuras con hilos domésticas (cables coaxiales, línias de teléfono y línias de electricidad) en un sólo estándar para la transmisión de datos hasta 1 Gb/s. La recomendación G.hn define una red unificada sobre línias de electricidad, de teléfono y coaxiales con diferentes esquemas para banda base y RF. El esquema RF-coax en el cual se basa esta tesis, usa canales con un ancho de banda de 50 MHz y 100 MHz con 256 y 512 portadoras respectivamente. La frecuencia centra puede variar desde 350 MHz hasta 2450 MHz. La recomendación especifica un límite en la potencia de transmisión de 5 dBm para el esquema de 50 MHz y 8 dBm para el esquema de 100 MHz, de tal forma que la potencia máxima por portadora es la misma en ambos esquemas. Debido a la estructura de un entorno doméstico con hilos, los receptores deben ser capaces de procesar señales con amplitud muy grande o muy pequeña; cuando transmisor y receptor están conectados en la misma toma eléctrica no hay atenuación de canal y el ratio de señal a rudio más distorsión (SNDR) está dominado por la linealidad del receptor, mientras que cuando transmisor y receptor están separados por varias habitaciones la atenuación es elevada y el SNDR está dominado por la figura de ruido del receptor. Los elevados requisitos de rango dinámico para este tipo de receptores requieren el uso de topologías de ganancia configurable que pueden proporcionar tanto alta linealidad como bajo ruido para diferentes configuraciones. Por lo tanto, esta tesis está encarada a la investigación de topologías sin inductores de banda ancha y elevado rango dinámico para ser usadas a la entrada de un receptor G.hn cumpliendo con las especificaciones proporcionadas. Una gran parte de la tesis se ha centrado en el diseño del amplificador de entrada al ser la etapa más crítica, ya que la figura de ruido y linealidad del amplificador de entrada definen lás máximas especificaciones que el sistema puede conseguir. Se han fabricado 3 prototipos con un proceso CMOS de 65 nm: 2 amplificadores y un sistema completo con amplificador y mezclador.Postprint (published version

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively

Amplificador de potência CMOS em 2.4 ghz com potência de saída programável

Orientador : Prof. Dr. Bernardo Rego Barros de Almeida LeiteCoorientador : Prof. Dr. André Augusto MarianoDissertação (mestrado) - Universidade Federal do Paraná, Setor de Tecnologia, Programa de Pós-Graduação em Engenharia Elétrica. Defesa: Curitiba, 12/12/2016Inclui referências : f. 89-90Área de concentraçãoResumo: A potência DC (PDC) em um sistema móvel sem fio é um critério deter-minante de projeto. O amplificador de potência (PA) é um dos subsistemas que mais consome PDC, uma vez que é responsável por amplificar sinais de baixa potência para sinais de alta potência de saída (POUT). Para que o uso da PDC seja eficiente, o sistema transmissor deve ser capaz de selecionar os níveis de POUT do PA conforme a necessidade da aplicação, relacionando de maneira ótima PDC e POUT. Em arquiteturas de PAs nas quais não é possível selecionar a POUT, o consumo da PDC é aproximadamente constante, independente da POUT utilizada. Dessa maneira, se a aplicação demanda uma POUT baixa, a PDC consumida será aproximadamente a mesma que aquela consumida por uma POUT alta. Ao contrário, em arquiteturas de PAs nas quais a POUT é selecioná-vel, o consumo da PDC é modulado conforme a demanda da POUT. Dessa ma-neira, se é necessária uma POUT alta, a PDC consumida será proporcionalmente maior. Se a POUT é baixa, a PDC consumida será proporcionalmente menor. O fato da PDC ser modulada em função da POUT caracteriza a utilização inteligente da energia disponível em um sistema móvel sem fio. Essa dissertação de mestrado apresenta o projeto, a implementação e a caracterização de um PA em tecnologia CMOS 130 nm em 2,4 GHz com POUT selecionável. O projeto do PA consiste em compreender o que é um PA, qual o seu papel e impacto em um sistema transmissor, onde ele se insere em um sistema transceptor de rádio frequências (RF) e em quais padrões de comunicação sem fio ele se enquadra. Também são demandas de projeto o estudo da tecnologia utilizada (características e ferramentas), CMOS RF8-DM, quais os benefícios e desafios encontrados na microeletrônica de potência em RF, quais arquiteturas atendem aos requisitos de projeto, acompanhar um tape-out, e determinar quais são as métricas utilizadas para a caracterização do circuito. A implementação, por sua vez, consiste em estudar a literatura referen-te às topologias de PAs com POUT selecionável, em compreender os blocos construtivos de um PA, em propor a captura de esquemático da solução defini-da, em realizar o leiaute e simulações do circuito. Por fim, a caracterização neste trabalho consiste em apresentar os re-sultados pós-leiaute e medições preliminares; em apresentar a comparação entre os resultados de pós-leiaute e o estado da arte; a comparação entre os resultados pós-layout e medições; a análise de variações de processo, tensão e temperatura (PVT) e Monte Carlo do circuito, e a apresentação dos resulta-dos do PA em alguns padrões de comunicação digital. Diferentemente da literatura estudada, o PA proposto utiliza um estágio de potência composto por três células de amplificação que são ativadas ou de-sativadas independentemente. Dependendo da combinação em que tais célu-las são ativadas ou desativadas, sete níveis diferentes de POUT e de PDC são obtidos. Por exemplo: quando todas as células são ativadas, o PA é capaz de entregar a maior faixa de POUT possível, entretanto, o consumo de PDC é tam-bém o maior. De forma contrária, se apenas uma célula for ativada e as demais desativadas, a faixa de POUT e o consumo de PDC são reduzidos. Dessa manei-ra, é possível adequar o PA para uma operação com consumo de PDC mínima dependente da POUT desejada. O circuito proposto possui sete modos de ope-ração unívocos em termos de ganho de pequeno sinal, ponto de compressão de 1 dB referenciado à potência de saída (OCP1dB) e potência saturada (PSAT). O PA é incondicionalmente estável em todos os modos de operação. O PA proposto é totalmente integrado, significando que componente externo algum é necessário para o seu funcionamento. Os blocos-núcleo do circuito são: rede de adaptação de impedância de entrada, estágio de ganho, componente de acoplamento interestágios, estágio de potência reconfigurável e rede de adaptação de impedância de saída. Os blocos periféricos do projeto são um buffer e um circuito gerador de polarização. O circuito é composto por pads para que seja possível aplicar e ler as tensões e sinais de RF. As redes de adaptação de impedância de entrada e de saída são responsáveis por adaptar a impedância de 50 ? à impedância de entrada do estágio de ganho e a impedância de saída do estágio de potência a 50 ?, respectivamente. Os estágios de ganho e de potência são responsáveis respectivamente por dar ganho de potência ao sinal RF de entrada e fornecer um sinal de saída com alta potência e baixas distorções. Ambos estágios são baseados em transisto-res em topologia cascode: a fonte de um transistor em configuração fonte co-mum (CS) conectada ao dreno de um transistor em configuração porta comum (CG). Em especial no estágio de potência, para se selecionar os diferentes modos de operação, as células cascode de potência devem ser ligadas ou des-ligadas. Para que as células sejam ligadas, deve-se aplicar a tensão VDD nas portas dos CGs. De forma contrária, para que as células cascode de potência sejam desligadas, deve-se aplicar a tensão gnd nas portas dos CGs. O leiaute do circuito foi realizado considerando a presença de parasitas dos metais, o fluxo e intensidade da corrente RF, o desacoplamento da interfe-rência RF na alimentação e a dispersão de potenciais de terra e de alimenta-ção por todo o circuito. Nenhum erro impactante de fabricação foi encontrado durante o design rule check e o layout Vs. schematic e a verificação de modo ortogonal não apresentaram erros. Após o leiaute, as componentes parasitas R e C foram extraídas, o arquivo de fabricação encaminhado para a MOSIS e simulações pós-leiaute foram conduzidas. A simulação pós-leiaute apresentou os seguintes resultados para o modo de menor potência: PSAT de 8,1 dBm, ganho de 13,5 dB e consumo de PDC de 171 mW para entregar 6 dBm de OCP1dB. O modo de maior potência, por sua vez, apresentou PSAT de 18,9 dBm, ganho de 21,1 dB e PDC de 415 mW para OCP1dB de 18,2 dBm. Em relação à literatura estudada, este trabalho pos-sui a maior faixa de OCP1dB e de PSAT. Em termos de medição, apenas o modo de operação de maior potência foi medido. Ele apresenta um PSAT de 12,6 dBm, OCP1dB de 9,4 dBm, ganho de 12,8 dB e PDC de 252 mW para o OCP1dB. Em termos comparativos, o modo de maior potência medido situou-se entre os modos de menor potência de simulação pós-leiaute. Na tentativa de determinar a fonte da diferença entre o circuito medido e simulado, algumas hipóteses foram testadas, tais como alteração da tensão de polarização do cir-cuito, métodos alternativos para extração de parasitas e influência dos pads no descasamento de impedâncias. Os resultados obtidos não foram suficientes para explicar a discrepância encontrada e espera-se que com as medições fal-tantes seja possível determinar a fonte de diferenças. Palavras-chave: Amplificador de potências. PA CMOS em 2,4 GHz. Po-tência de saída selecionável.Abstract: The DC power consumption (PDC) of a mobile wireless system is a de-terminant project criterion. The power amplifier (PA) is one of the most PDC con-suming subsystem, as it is responsible for amplifying low power signals into high output power (POUT) signals. In order to use PDC efficiently, the transmitter system must be capable of selecting levels of POUT according to the amplifica-tion demand, optimizing the PDC and POUT relation. This masters dissertation presents the design, implementation and characterization of a selectable POUT 2.4 GHz 130 nm CMOS PA. Employing a power stage composed of amplifica-tion cells that are independently enabled or disabled, different levels of POUT and PDC are achieved. The designed amplifier is composed of seven univocal power modes and is fully integrated, meaning that no external components are needed for operation. The characterization of the circuit is composed of small and large-signal continuous-wave metrics, as well as digital channel metrics. The post-layout simulations showed a lowest power mode with a PSAT of 8.1 dBm, gain of 13.5 dB and PDC consumption of 171 mW to deliver an OCP1dB of 6 dBm. The highest power mode performs a PSAT of 18.9 dBm, gain of 21.1 dB and PDC of 415 mW for an 18.2 dBm OCP1dB. The circuit was fabricated and preliminary measurements were conducted. The comparison between measurement and simulation results showed that the fabricated circuit performs bellow expected. Some hypotheses and tests were conducted to determine the difference, but no conclusive results were obtained as further measurements are necessary. Key-words: Power amplifier. 2.4 GHz CMOS PA. Selectable output power

Design and Analysis of Low-power Millimeter-Wave SiGe BiCMOS Circuits with Application to Network Measurement Systems

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 17

A Low-Power Wireless Multichannel Microsystem for Reliable Neural Recording.

This thesis reports on the development of a reliable, single-chip, multichannel wireless biotelemetry microsystem intended for extracellular neural recording from awake, mobile, and small animal models. The inherently conflicting requirements of low power and reliability are addressed in the proposed microsystem at architectural and circuit levels. Through employing the preliminary microsystems in various in-vivo experiments, the system requirements for reliable neural recording are identified and addressed at architectural level through the analytical tool: signal path co-optimization. The 2.85mm×3.84mm, mixed-signal ASIC integrates a low-noise front-end, programmable digital controller, an RF modulator, and an RF power amplifier (PA) at the ISM band of 433MHz on a single-chip; and is fabricated using a 0.5µm double-poly triple-metal n-well standard CMOS process. The proposed microsystem, incorporating the ASIC, is a 9-channel (8-neural, 1-audio) user programmable reliable wireless neural telemetry microsystem with a weight of 2.2g (including two 1.5V batteries) and size of 2.2×1.1×0.5cm3. The electrical characteristics of this microsystem are extensively characterized via benchtop tests. The transmitter consumes 5mW and has a measured total input referred voltage noise of 4.74µVrms, 6.47µVrms, and 8.27µVrms at transmission distances of 3m, 10m, and 20m, respectively. The measured inter-channel crosstalk is less than 3.5% and battery life is about an hour. To compare the wireless neural telemetry systems, a figure of merit (FoM) is defined as the reciprocal of the power spent on broadcasting one channel over one meter distance. The proposed microsystem’s FoM is an order of magnitude larger compared to all other research and commercial systems. The proposed biotelemetry system has been successfully used in two in-vivo neural recording experiments: i) from a freely roaming South-American cockroach, and ii) from an awake and mobile rat.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91542/1/aborna_1.pd

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Development of a broadband and squint-free Ku-band phased array antenna system for airborne satellite communications

Novel avionic communication systems are required for various purposes, for example to increase the flight safety and operational integrity as well as to enhance the quality of service to passengers on board. To serve these purposes, a key technology that is essential to be developed is an antenna system that can provide broadband connectivity within aircraft cabins at an affordable price. Currently, in the European Commission (EC) 7th Framework Programme SANDRA project (SANDRA, 2011), a development of such an antenna system is being carried out. The system is an electronically-steered phased-array antenna (PAA) with a low aerodynamic profile. The reception of digital video broadcasting by satellite (DVB-S) signal which is in the frequency range of 10.7-12.75 GHz (Ku-band) is being considered. In order to ensure the quality of service provided to the passengers, the developed antenna should be able to receive the entire DVB-S band at once while complying with the requirements of the DVB-S system (Morello & Mignone, 2006). These requirements, as will be explained later, dictate a broadband antenna system where the beam is squint-free, i.e. no variation of beam pointing direction for all the frequencies in the desired band. Additionally, to track the satellite, the seamless tunability of the beam pointing direction of this antenna is also required. In this work, a concept of optical beamforming (Riza & Thompson, 1997) is implemented to provide a squint-free beam over the entire Ku-band for all the desired pointing directions. The optical beamformer itself consists of continuously tunable optical delay lines that enable seamless tunability of the beam pointing direction

Low-noise amplifiers for integrated multi-mode direct-conversion receivers

The evolution of wireless telecommunication systems during the last decade has been rapid. During this time the design driver has shifted towards fast data applications instead of speech. In addition, the different systems may have a limited coverage, for example, limited to urban areas only. Thus, it has become important for a mobile terminal to be able to use different wireless systems, depending on the application chosen and the location of the terminal. The choice of receiver architecture affects the performance, size, and cost of the receiver. The superheterodyne receiver has hitherto been the dominant radio architecture, because of its good sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which, with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore, architectures using a minimum number of external components, such as direct conversion, have become popular. In addition, compared to the superheterodyne architecture, the direct-conversion architecture has benefits when multi-mode receivers, which are described in this thesis, are being designed. In this thesis, the limitations placed on the analog receiver by different system specifications are introduced. The estimations for the LNA specifications are derived from these specifications. In addition, the limitations imposed by different types of receiver architectures are described. The inductively-degenerated LNA is the basis for all the experimental circuits. The different components for this configuration are analyzed and compared to other commonly-used configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed. Without knowing these limitations, it becomes difficult to understand the choices made in the experimental circuits. One of the key parts of this thesis describes the design and implementation of a single-chip multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode structures in this thesis were developed for a direct-conversion receiver where only one system is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different LNA components are analyzed in detail. Furthermore, the design issues related to possible interference from additional systems on single-chip receivers are analyzed and demonstrated. A typical receiver includes variable gain, which can be implemented both in the analog baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically placed in the LNA or in a separate gain control stage. Several methods that can be used to implement a variable gain in the LNA are introduced and compared to each other. Furthermore, several of these methods are included in the experimental circuits. The last part of this thesis concentrates on four experimental circuits, which are described in this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D converters on the same chip as sensitive RF blocks without significantly degrading receiver performance. The other two chips describe an RF front-end for WCDMA and GSM900 applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA systems. These ICs demonstrate the usability of the circuit structure developed and presented in this thesis. The chip area in the last multi-mode receiver is not significantly increased compared to corresponding single-system receivers.reviewe