64 research outputs found
Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers
Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile
phone, enabling data to be sent over the distances needed to reach the receiver’s antenna.
While linear operation is needed for transmitting WCDMA and OFDM signals, linear
operation of a power amplifier is characterized by low power efficiency, and contributes
to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier
operation was considered for reducing power losses in a RF transmitter. A linear and
efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu-
lated, and subsequently amplified by a nonlinear device. Although in theory this approach
offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting
wideband signals causes problems in practical implementation: it requires high sampling
rate by the digital hardware, which is needed for shaping large contents of a quantization
noise induced by the modulator but also, the binary output from the modulator needs an
RF power amplifier operating over very wide frequency band.
This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear
distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ
modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved
by optimizing structure of the modulator, and subsequent processing of an input signal’s
samples in parallel. Independent from the above, a novel technique for reducing quan-
tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The
technique combines error pulse shaping and 3-level quantization for improving signal to
noise ratio in a 2-level output. The improvement is achieved without the increase of a digital
hardware’s sampling rate, which is advantageous also from the perspective of power
consumption. The new method is explored in the course of analysis, and verified by simulated
and experimental results. The process of RF signal conversion from the Cartesian to
polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized
envelope signal is designed and implemented. The new modulator takes an advantage of
bandpass digital to analog conversion for simplifying the analog part of the modulator.
A deformation of the pulsed RF signal in the experimental modulator is demonstrated to
have an effect primarily on amplitude of the RF signal, which is correctable with simple
predistortion
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Design techniques for wideband low-power Delta-Sigma analog-to-digital converters
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations of a ΔΣ modulator. One is based on the discrete-time (DT) switched-capacitor (SC) circuitry and the other employs continuous-time (CT) circuitry. Compared to a CT
structure, the DT ΔΣ ADC is easier to analyze and design, is more robust to process variations and jitter noise, and is more flexible in the multi-mode applications. On the other hand, the CT ΔΣ ADC does not suffer from the strict settling accuracy requirement for the loop filter and thus can achieve lower power dissipation and higher sampling frequency than its DT counterpart.
In this thesis, both DT and CT ΔΣ ADCs are investigated. Several design innovations, in both system-level and circuit-level, are proposed to achieve lower power consumption and wider signal bandwidth.
For DT ΔΣ ADCs, a new dynamic-biasing scheme is proposed to reduce opamp bias current and the associated signal-dependent harmonic distortion is minimized by using the low-distortion architecture. The technique was verified in a 2.5MHz BW and 13bit dynamic range DT ΔΣ ADC. In addition, a second-order noise coupling technique is presented to save two integrators for the loop filter, and to achieve low power dissipation. Also, a direct-charge-transfer (DCT) technique is suggested to reduce the speed requirements of the adder, which is also preferable in wideband low-power applications.
For CT ΔΣ ADCs, a wideband low power CT 2-2 MASH has been designed. High linearity performance was achieved by using a modified low-distortion technique, and the modulator achieves higher noise-shaping ability than the single stage structure due to the inter-stage gain. Also, the quantization noise leakage due to analog circuit non-idealities can be adaptively compensated by a designed digital calibration filter. Using a 90nm process, simulation of the modulator predicts a 12bit resolution within 20MHz BW and consumes only 25mW for analog circuitry. In addition, the noise-coupling technique is investigated and proposed for the design of CT ΔΣ ADCs and it is promising to achieve low power dissipation for wideband applications.
Finally, the application of noise-coupling technique is extended and introduced to high-accuracy incremental data converters. Low power dissipation can be expected
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Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters
There is a significant need in recent mobile communication and wireless broadband
systems for high-performance analog-to-digital converters (ADCs) that have wide
bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is
recognized as a power-efficient ADC architecture when high resolution (>12-b) is
required. This is due to several advantages of the delta-sigma ADC including relaxed
anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and
most importantly, reduced sensitivity to analog imperfections. In this thesis, several
structures and design techniques are developed for the implementation of continuoustime
(CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total
power consumption, reduce the design complexity, and decrease the chip die area of
delta-sigma modulators.
First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad
(SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of
an Nth-order CT delta-sigma modulator, it requires only half the number of active
amplifiers and feed-forward branches used in the conventional modulator architecture,
thus decreasing the power consumption and area by reducing the number of amplifiers.
The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder
due to the reduced number of feedforward branches to its summing block. As a sequence,
it consumes less power compared to a conventional CT adder. With a 130-nm CMOS
technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz
signal bandwidth and analog power dissipation lower than 12 mW. Presented as the
second scheme to save power consumption and chip die area in ΔΣ modulators is a new
stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique
shares all the active blocks of the modulator second stage with its first stage during the
two non-overlapping clock phases. Measurement results show that the modulator
designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz
conversion bandwidth dissipating less than 9 mW analog power
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Low-power double-sampled delta-sigma modulator for broadband applications
High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance ΔΣ ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled ΔΣ modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization.
Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion ΔΣ modulator. A second-order ΔΣ modulator was designed and simulated to verify the proposed modulator topology.
Finally, design of a double-sampled broadband 12-bit ΔΣ modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques:
1. Double sampled integrator to increase the effective over-sampling ratio.
2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back.
A 2+2 cascaded topology with 3-bit internal quantizer is used in this ΔΣ modulator to adequately suppress the quantization noise while guarantee the loop stability. This ΔΣ modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm² and consumes 10mW with a supply voltage of 1.2V
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el tÃtulo de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologÃas móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topologÃa sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en IngenierÃa Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: MarÃa Luisa López Vallejo.- Vocal: Pieter Rombout
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A survey on continuous-time modulators : theory, designs and implementations
Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
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