There is a significant need in recent mobile communication and wireless broadband
systems for high-performance analog-to-digital converters (ADCs) that have wide
bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is
recognized as a power-efficient ADC architecture when high resolution (>12-b) is
required. This is due to several advantages of the delta-sigma ADC including relaxed
anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and
most importantly, reduced sensitivity to analog imperfections. In this thesis, several
structures and design techniques are developed for the implementation of continuoustime
(CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total
power consumption, reduce the design complexity, and decrease the chip die area of
delta-sigma modulators.
First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad
(SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of
an Nth-order CT delta-sigma modulator, it requires only half the number of active
amplifiers and feed-forward branches used in the conventional modulator architecture,
thus decreasing the power consumption and area by reducing the number of amplifiers.
The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder
due to the reduced number of feedforward branches to its summing block. As a sequence,
it consumes less power compared to a conventional CT adder. With a 130-nm CMOS
technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz
signal bandwidth and analog power dissipation lower than 12 mW. Presented as the
second scheme to save power consumption and chip die area in ΔΣ modulators is a new
stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique
shares all the active blocks of the modulator second stage with its first stage during the
two non-overlapping clock phases. Measurement results show that the modulator
designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz
conversion bandwidth dissipating less than 9 mW analog power