A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

Decoupled Thermal Simulation

Small transistors and high clock frequency have resulted in high power density, which makes temperature a strong constraint in today's microprocessor design. For maximizing performance, the thermal design power must be set according to average, instead of worst case, conditions. Consequently, current processors feature temperature sensors and throt-tling mechanisms to keep the chip temperature at a safe level. To study future thermally-constrained processors and systems, researchers and engineers use cycle-accurate performance simulators modeling power consumption and temperature. Cycle-accurate simulators are relatively slow and make it difficult to study long-term thermal behaviors that may require to simulate several minutes or even hours of processor execution. Sampling or phase analysis cannot be applied directly in this case because temperature depends on all past energy events. We propose a partial solution to this problem, which consists in decoupling cycle-accurate simulations and thermal ones. Temperature-unaware cycle-accurate simulation is used to generate an energy trace representing the complete execution of an application. Phase analysis can be used to decrease the trace generation time and make compact traces. Temperature and thermal-throttling are simulated in a separate thermal simulator that reads energy traces. The thermal simulator is faster than the cycle-accurate one and can be used to explore, with the same energy trace, parameters that are not modeled in cycle-accurate simulation

Approaches to multiprocessor error recovery using an on-chip interconnect subsystem

For future multicores, a dedicated interconnect subsystem for on-chip monitors was found to be highly beneficial in terms of scalability, performance and area. In this thesis, such a monitor network (MNoC) is used for multicores to support selective error identification and recovery and maintain target chip reliability in the context of dynamic voltage and frequency scaling (DVFS). A selective shared memory multiprocessor recovery is performed using MNoC in which, when an error is detected, only the group of processors sharing an application with the affected processors are recovered. Although the use of DVFS in contemporary multicores provides significant protection from unpredictable thermal events, a potential side effect can be an increased processor exposure to soft errors. To address this issue, a flexible fault prevention and recovery mechanism has been developed to selectively enable a small amount of per-core dual modular redundancy (DMR) in response to increased vulnerability, as measured by the processor architectural vulnerability factor (AVF). Our new algorithm for DMR deployment aims to provide a stable effective soft error rate (SER) by using DMR in response to DVFS caused by thermal events. The algorithm is implemented in real-time on the multicore using MNoC and controller which evaluates thermal information and multicore performance statistics in addition to error information. DVFS experiments with a multicore simulator using standard benchmarks show an average 6% improvement in overall power consumption and a stable SER by using selective DMR versus continuous DMR deployment

Sensor de temperatura CMOS integrado

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaEste trabalho apresenta um sensor de temperatura CMOS integrado voltado ao monitoramento de hot-spots em circuitos VLSI. Seu funcionamento é baseado no comportamento CTAT (complementar a temperatura absoluta) da tensão de limiar do transistor MOS. Devido a este fato, inicia-se a dissertação apresentando alguns métodos utilizados na extração deste parâmetro através de simulações. Em seguida, medições realizadas em alguns transistores de teste servem para validar os resultados obtidos nas simulações. O projeto do sensor é, então, apresentado detalhando-se seus blocos constituintes separadamente: gerador de corrente específica, comparador e gerador do pulso de saída. Em todos os blocos tomou-se o cuidado para que o consumo total do sensor fosse na ordem de poucas dezenas de microwatts de modo a possibilitar o instanciamento de diversos elementos para o mapeamento térmico de um microprocessador. O gerador de corrente específica foi utilizado para fornecer tanto uma corrente quanto uma tensão de referência. A simulação do sensor completo apresentou um consumo de 18mW no pior caso a 120°C. A área total do sensor foi de 0,006mm² em uma tecnologia de 0,18µm. Medições de três amostras do protótipo fabricado demonstraram que a corrente apresentou discrepância de aproximadamente 5% de chip para chip e, no pior caso, variação de 4% na faixa de 0°C a 100°C. Uma variação máxima de chip para chip de 13mV, a 20°C, foi medida na tensão de referência, apresentando todas as amostras uma faixa dinâmica de 170mV de 0°C a 100°C, com um erro médio máximo na linearidade com respeito à temperatura de 1,87°C na faixa de 20°C a 100°C.This work presents a CMOS integrated temperature sensor aiming at monitoring hot-spots in microprocessors. Its principle is based on the CTAT dependance of the threshold voltage of the MOS transistor. Therefore, we start showing some threshold voltage extraction procedures with their results being validated through measurements in test transistors. The design of the main sesnsor blocks, namely, specific currente generator, comparator and pulse generator is presented. The total sensor power consumption was kept close to a few of tens of microwatts in order to allow the placement of various sensor elements in a microprocessor. The specific current generator provides both current and voltage references. The simulation indicated a power consumption of 18mW in the worst case at 120°C. The total area was 0.006mm2 in a 0.18um technology. Measurements on three samples showed a chip-to-chip variation around 5% for the reference current and, in the worst case, 4% variation from 0°C to 100°C. The reference voltage presented maximum 13mV at 20°C variation for chip-to-chip and, for 3 samples, a variation around 170mV from 0°C to 100°C and a maximum average linearity error equals to 1.87°C in 20°C to 100°C range

Système de mesure de la température d'un processeur en temps réel par thermographie infrarouge

RÉSUMÉ L’analyse thermique de tout composant électronique est souvent limitée par l’incapacité d’obtention de données de température précises et détaillées. Ainsi la validation des modèles thermiques élaborés pour décrire le comportement des microprocesseurs se fait soit par simulation sans la mesure en temps réel des réponses de chaque composant soit via l’utilisation des thermocouples comme méthode de collecte de données dans des zones spécifiques de la puce. Les deux méthodes présentent certaines lacunes: La simulation est fondée sur des modèles imparfaits tandis que la collecte des données ne peut pas donner des valeurs précises de la température. Pour résoudre ce problème, la mise en place d’une nouvelle méthodologie de validation de modèle de simulation a fait l’objet de ce travail. Cette méthodologie consiste à l’utilisation de la thermographie IR pour la capture de la distribution de la température et la dissipation de la puissance d’une puce en temps réel. L’installation d’un tel système de mesure nécessite le remplacement du système de refroidissement installé sur le processeur par un autre système permettant le passage des radiations IR qui seront détectées par la caméra infrarouge. Pour ce faire, nous avons eu recours à deux solutions, l’utilisation de l’huile minérale et le module à effet de Peltier. Les meilleurs résultats ont été obtenus avec la deuxième solution proposée qui a permis un meilleur contrôle et une stabilisation de la température. Les résultats montrent que les deux ICTherm et Comsol fournissent des valeurs de température qui se trouvent dans la précision de la caméra infrarouge utilisé dans cette étude (± 2 ºC).----------ABSTRACT The thermal analysis of any electronic component is often limited by the inability to obtain detailed and accurate temperature data. To validate any thermal model developed to describe the behavior of microprocessors, two methods are currently used. One technique simulates the thermal response of each component given a certain input; the other uses thermocouples as a method of data collection in specific chip areas. Both methods have various shortcomings: simulation relies on imperfect models, while data collection cannot provide fine-grained temperature values. To solve this problem, we investigated the establishment of a new methodology to validate a thermal simulation model. It involves the use of infrared thermography to capture the distribution of temperature and the power dissipation of a chip in real time. The installation of such a measurement system requires the replacement of the cooling system installed on the processor by another system which enables the passage of IR radiation to be detected by the camera. Two solutions were proposed, the use of mineral oil and a thermoelectric cooler (a Peltier module). The best results were obtained with the latter, allowing better control and temperature stabilization. The data collected by our system were then used to validate the accuracy of the thermal of two thermal models, Comsol and ICTherm. Results show that both ICTherm and Comsol provide temperature values that are within the accuracy of the infrared camera used in this study, i.e. ± 2 ºC

IC design for reliability

textAs the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level. A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closedform expression. Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage. In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTIinduced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for costeffective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system. The developed methods improve the over-conservatism of the device-level, worstcase reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods.Electrical and Computer Engineerin

In-situ and In-field temperature and transistor BTI sensing techniques with microprocessor level implementation

In modern deep-scaled CMOS technologies, various silicon-related pitfalls present challenges to the long-term performance of microprocessors. Such challenges include (1) local hot spots, which breach the thermal limitations of a microprocessor, and (2) transistor aging, especially NBTI, which degrades transistor threshold voltage, ultimately threatening the reliability of the entire memory block. In previous systems, the dummy circuit was placed next to the subject, where the dummy was frequently analyzed, and the readout was used to infer the condition of the target. Due to rapidly changing ambient conditions (e.g., temperature and voltage) and the potential scale of the target dimensions, such metrics may not accurately represent the condition of the target. Moreover, such temperature sensors and canary circuits occupy a significant area. Therefore, it would be highly preferable to monitor the target circuit in-situ, i.e., to sense the precise transistor at operation. It is also important to achieve an accurate sensing metric. When the temperature is analyzed, the readout should account for voltage and process variations. While sensing the aging degradation, the readout should account for voltage and temperature fluctuations. This would allow testing during in-field operation, while the circuits achieve area-efficiency. This research had two stages. One result of the first stage was a silicon test chip that was a compact temperature sensor. It involved a family of PTAT+CTAT sensor front-ends that unitized only 6 to 8 conventional CMOS logic devices, yielding a smaller sized chip. The sensor demonstrates accuracy within the target and achieves a 14.3x smaller foot print than preceding published designs. The second product of the first stage was a PMOS aging sensor used in 6T SRAM circuits. The test chip has a real SRAM array, integrated with the proposed PMOS NBTI sensor. It can sense real PMOS NBTI effects in any bit cell (in-situ) and provide robust readings of temperature and voltage (in-field). Intensive aging tests validated the proposed sensing technique. The second stage was focused on implementing the in-situ and in-field sensing techniques in a real processor. The MIPS microprocessor had a modified instruction cache (I$) and instruction set architecture. With the addition of new instruction aging sensing and minor modification of the circuits, the processor can execute aging sensing opportunistically to evaluate the aging level of its instruction cache. A software framework was developed and verified to estimate the retention voltage of the instruction cache over the lifetime of the chip. An area-efficient SoC was developed that could transform the instruction cache into an ambient temperature sensor. It had a physically unclonable function (PUF), and it was built with an area-saving technique similar to the earlier work. This thesis has four chapters. They are presented in chronological and they are aligned with the research described above

CPU accounting in multi-threaded processors

In recent years, multi-threaded processors have become more and more popular in industry in order to increase the system aggregated performance and per-application performance, overcoming the limitations imposed by the limited instruction-level parallelism, and by power and thermal constraints. Multi-threaded processors are widely used in servers, desktop computers, lap-tops, and mobile devices. However, multi-threaded processors introduce complexities when accounting CPU (computation) capacity (CPU accounting), since the CPU capacity accounted to an application not only depends upon the time that the application is scheduled onto a CPU, but also on the amount of hardware resources it receives during that period. And given that in a multi-threaded processor hardware resources are dynamically shared between applications, the CPU capacity accounted to an application in a multi-threaded processor depends upon the workload in which it executes. This is inconvenient because the CPU accounting of the same application with the same input data set may be accounted significantly different depending upon the workload in which it executes. Deploying systems with accurate CPU accounting mechanisms is necessary to increase fairness among running applications. Moreover, it will allow users to be fairly charged on a shared data center, facilitating server consolidation in future systems. This Thesis analyses the concepts of CPU capacity and CPU accounting for multi-threaded processors. In this study, we demonstrate that current CPU accounting mechanisms are not as accurate as they should be in multi-threaded processors. For this reason, we present two novel CPU accounting mechanisms that improve the accuracy in measuring the CPU capacity for multi-threaded processors with low hardware overhead. We focus our attention on several current multi-threaded processors, including chip multiprocessors and simultaneous multithreading processors. Finally, we analyse the impact of shared resources in multi-threaded processors in operating system CPU scheduler and we propose several schedulers that improve the knowledge of shared hardware resources at the software level