Energy challenges for ICT

The energy consumption from the expanding use of information and communications technology (ICT) is unsustainable with present drivers, and it will impact heavily on the future climate change. However, ICT devices have the potential to contribute signi - cantly to the reduction of CO2 emission and enhance resource e ciency in other sectors, e.g., transportation (through intelligent transportation and advanced driver assistance systems and self-driving vehicles), heating (through smart building control), and manu- facturing (through digital automation based on smart autonomous sensors). To address the energy sustainability of ICT and capture the full potential of ICT in resource e - ciency, a multidisciplinary ICT-energy community needs to be brought together cover- ing devices, microarchitectures, ultra large-scale integration (ULSI), high-performance computing (HPC), energy harvesting, energy storage, system design, embedded sys- tems, e cient electronics, static analysis, and computation. In this chapter, we introduce challenges and opportunities in this emerging eld and a common framework to strive towards energy-sustainable ICT

Towards Oxide Electronics:a Roadmap

At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore's law is approaching the insurmountable barrier given by the ultimate atomic nature of matter. A major challenge for 21st century scientists is finding novel strategies, concepts and materials for replacing silicon-based CMOS semiconductor technologies and guaranteeing a continued and steady technological progress in next decades. Among the materials classes candidate to contribute to this momentous challenge, oxide films and heterostructures are a particularly appealing hunting ground. The vastity, intended in pure chemical terms, of this class of compounds, the complexity of their correlated behaviour, and the wealth of functional properties they display, has already made these systems the subject of choice, worldwide, of a strongly networked, dynamic and interdisciplinary research community. Oxide science and technology has been the target of a wide four-year project, named Towards Oxide-Based Electronics (TO-BE), that has been recently running in Europe and has involved as participants several hundred scientists from 29 EU countries. In this review and perspective paper, published as a final deliverable of the TO-BE Action, the opportunities of oxides as future electronic materials for Information and Communication Technologies ICT and Energy are discussed. The paper is organized as a set of contributions, all selected and ordered as individual building blocks of a wider general scheme. After a brief preface by the editors and an introductory contribution, two sections follow. The first is mainly devoted to providing a perspective on the latest theoretical and experimental methods that are employed to investigate oxides and to produce oxide-based films, heterostructures and devices. In the second, all contributions are dedicated to different specific fields of applications of oxide thin films and heterostructures, in sectors as data storage and computing, optics and plasmonics, magnonics, energy conversion and harvesting, and power electronics

Scaling silicon-based quantum computing using CMOS technology: State-of-the-art, Challenges and Perspectives

Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.Comment: Comments welcom

High Frequency Multiferroic Devices

This dissertation focuses on high frequency multiferroic devices from both theoretical and experimental aspects. Some potential applications for high frequency multiferroic: antennas, logic and memory, will be presented in this dissertation. The introduction section provides a fundamental explanation on the multiferroic devices as well as the modeling methods for strain-mediated multiferroic systems. Former researches indicate that the composites of piezoelectric substrate and the magnetoelastic material show great potential on reducing both the devices’ size as well as energy consumption.Part I of the dissertation shows multiferroics for antenna applications. Conventionally, antennas such as dipoles and loops rely on an electromagnetic (EM) wave resonance. Therefore, the sizes of such antennas are within the same order of free space wavelength. Multiferroic antenna can transfer the EM wave into an acoustic wave, which has much smaller wavelength compared with the wavelength of the EM wave under the same frequency. In this way, multiferroic antennas show a promising path for reducing the antenna system’s size, weight and volume. Also, three multiferroic antennas: shear wave antenna, lamb wave antenna as well as tunable frequency broadband antenna are introduced in this section. The shear wave antenna and lamb wave antenna are studied experimentally, and the tunable frequency broadband antenna is studied theoretically. All of them show great potential on reducing the antenna’s size.Part II of this dissertation indicates other applications of multiferroic devices: logic and memory. For the logic aspects, a numerical simulation is performed on in-plane mode Bennett clocking systems. For memory aspects, a new concept for breaking the switch symmetry the high frequency control of the magnetization in nanodisk. In this part, a fully coupled finite element model is used to simulate the switch process of the magnetization in the nanodisks. This voltage-controlled process has potential be used in magnetic memory devices with very low energy dissipations

Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Review on suitable eDRAM configurations for next nano-metric electronics era

We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.Peer ReviewedPostprint (author's final draft

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

This thesis focuses mainly on the co-integration of vertical nanowiren-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), whereMOVPE grown vertical InAs-GaSb heterostructure nanowires areused for realizing monolithically integrated and co-processed all-III-V CMOS.Utilizing a bottom-up approach based on MOVPE grown nanowires enablesdesign flexibilities, such as in-situ doping and heterostructure formation,which serves to reduce the amount of mask steps during fabrication. By refiningthe fabrication techniques, using a self-aligned gate-last process, scaled10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabledby greatly improved p-type MOSFET performance reaching a maximumtransconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipationfor CMOS circuits requires good threshold voltage VT matching of the n- andp-type device, which is also demonstrated for basic inverter circuits. Thevarious effects contributing to VT-shifts are also studied in detail focusing onthe InAs channel devices (with highest transconductance of 2.6 mA/μm), byusing Electron Holography and a novel gate position variation method (PaperV).The advancements in all-III-V CMOS integration spawned individual studiesinto the strengths of the n- and p-type III-V devices, respectively. Traditionallymaterials such as InAs and InGaAs provide excellent electrontransport properties, therefore they are frequently used in devices for highfrequency RF applications. In contrast, the III-V p-type alternatives have beenlacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFETchannel, was designed and enabled by new manufacturing techniques, whichallowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs(Paper III). The new fabrication method allowed for integration of deviceswith symmetrical contacts as compared to previous work which relied on atunnel-contact at the source-side. By modelling based on measured data fieldeffecthole mobility of 70 cm2/Vs was calculated, well in line with previouslyreported studies on GaSb nanowires. The oxidation properties of the GaSbgate-stack was further characterized by XPS, where high intensities of xraysare achieved using a synchrotron source allowed for characterization ofnanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPSmeasurements, enabled a study of the time-dependence during full removalof GaSb native oxides.The last focus of the thesis was building on the existing strengths of verticalheterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,these devices demonstrate high-current densities (gm >3 mS/μm) and excellentmodulation properties (off-state current down to 1 nA/μm). However,minimizing the parasitic capacitances, due to various overlaps originatingfrom a low access-resistance design, has proven difficult. Therefore, newmethods for spacers in both the vertical and planar directions was developedand studied in detail. The new fabrication methods including sidewall spacersachieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which isthe established limit by optimized high-speed devices. The vertical spacertechnology, using SiO2 on the nanowire sidewalls, is further improved inthis thesis which enables new co-integration schemes for memory arrays.Namely, the refined sidewall spacer method is used to realize selective recessetching of the channel and reduced capacitance for large array memoryselector devices (InAs channel) vertically integrated with Resistive RandomAccess Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-memristor (1T1R) demonstrator cell shows excellent endurance and retentionfor the RRAM by maintaining constant ratio of the high and low resistive state(HRS/LRS) after 106 switching cycles