Design and VHDL Modeling of All-Digital PLLs

International audienceIn this paper, a VHDL model of a second-order alldigital phase-locked loop (ADPLL) based on bang-bang phase detectors is presented. The developed ADPLL is destined to be a part of a distributed clock generators based on networks of the ADPLL. The paper presents an original model and architecture of a digital multi-bit phase-frequency detector (PFD), and describes in details the VHDL modeling of metastability issues related with asynchronous operation of the digital PFD. This particular architecture of the digital PHD is required by the synchronised operation of the ADPLL network in the context of distributed clock generator. The whole ADPLL model have been validated by purely behavioral (VHDL) and mixed simulation, in which the digital PFD detector was represented by its transistorlevel model

An all-digital ΣΔ--frequency discriminator of arbitrary order

In this paper, we propose an all-digital frequency synthesizer architecture, based on an all-digital ΣΔ-frequency discriminator. The new all-digital synthesizer is compared to previously published work. The architecture of the ΣΔ-frequency discriminator is verified using behavioral simulation

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

Fractional Order and Virtual Variable Sampling Design of Repetitive Control for Power Converters

With the growth of electricity demand and renewable energy power source, power converter becomes a more and more significant component in electrical power systems. The requirement of the power converter controller is to produce an accurate and low-distorted voltage or current under different load conditions. Although the conventional controller can meet the requirement of some applications, it requires accurate knowledge of the system model and cannot provide a satisfactory result especially under nonlinear loads or sudden load change. Repetitive control (RC) presents an attractive solution to achieve excellent steady-state tracking error and low total harmonic distortion for periodic signals, and it is increasingly applied to power converter systems. However, there are still some limitations or requirements of RC when it is applied to power electronics system: first, RC requires the system sampling frequency is a fixed value and needs to be an integral multiple of the reference frequency; second, low controller sampling frequency results in low phase lead compensation resolution in RC, which leads to control inaccuracy; third, conventional RC does not have frequency adaptability to reference frequency fluctuation, and even a small reference frequency fluctuation can lead to severe performance degradation. To overcome the conventional RC limitations, two advanced design methods are proposed in the thesis: fractional order delay and virtual variable sampling. The method of fractional order delay approximates the non-integer delay part by building a finite impulse response filter. This improved method is not only able to be applied on a period delay unit but also on phase-lead compensation. The accurate period delay and phase lead compensation show a noticeable improvement in RC performance. Although fractional order delay can meet the requirement on most of the applications, it also has a minimal adjustable range on the reference frequency. To achieve an essential solution to this problem, the virtual variable sampling (VVS) method is developed. The VVS approximates a variable sampling unit instead of the fixed system unit for RC and its filters, in which RC is able to be frequency adaptive. Comparing with the method of fractional order delay, the VVS method can provide a much more extensive adjustable range on the reference frequency. Based on the system performance under the conventional controller, power converter always has uneven distortion distribution. To further improve the stability and eliminate harmonic distortions efficiently, two selective harmonic RC schemes are introduced - nk ± m order harmonic RC and DFT-based selective harmonic RC. However, these selective RC schemes also suffer from the particular requirement of system sampling frequency and low reference frequency adaptability. Applying VVS methods on these two schemes can effectively present an improvement on their frequency adaptability. To verify the proposed methods’ effectiveness, a complete series of power electronics applications are carried out. These applications include single-phase and three-phase DC/AC power converter, single-phase AC/DC power converter, and single-phase grid-connected power converter. The detailed system modeling and the proposed RC schemes are presented for each power electronics application

Design and investigation of nanometric integrated circuits for all-digital frequency synthesisers

Disertacijoje nagrinėjami daugiajuosčių dažnio sintezatorių blokai, modeliai bei jų kūrimas taikant nanometrines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad taikant nanometrines technologijas visiškai skaitmeniniai dažnio sintezatoriai įgalina gauti parametrus, reikiamus daugiajuosčiams belai- džio ryšio siųstuvams-imtuvams. Darbo tikslas – sukurti visiškai skaitmeninio dažnio sintezatoriaus blokus, kuriuos naudojant galima pasiekti reikiamus sinte- zatoriaus, skirto daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams, paramet- rus taikant nanometrines integrinių grandynų gamybos technologijas. Darbe išsp- ręsti tokie uždaviniai: ištirtos dažnio sintezatorių struktūros ir sukurta struktūra, tinkama įgyvendinti taikant nanometrines technologijas, sukurti ir ištirti siūlomos struktūros sintezatorių sudarančių blokų modeliai ir integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatū- ros ir autoriaus publikacijų disertacijos tema sąrašai ir keturi priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašo- mas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma ty- rimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, gi- namieji teiginiai bei disertacijos struktūra. Pirmajame skyriuje apžvelgiamos dažnio sintezatorių rūšys, aprašomi pag- rindiniai dažnio sintezatorių parametrai ir dažniausiai naudojamos kokybės funk- cijos. Apžvelgiami dažnio sintezatorių modeliai ir jų veikimas fazės ir dažnio sri- tyse. Aprašomi visiškai skaitmeninio dažnio sintezatoriaus triukšmų šaltiniai. Skyriaus pabaigoje suformuluojami disertacijos uždaviniai. Antrajame skyriuje pasiūlyta ir taikoma nauja kokybės funkcija, leidžianti at- likti daugiajuosčių dažnio sintezatorių palyginamąją analizę. Iškeliami reikalavi- mai pagrindiniams sintezatoriaus blokams, nagrinėjami laikinio skaitmeninio kei- tiklio skiriamosios gebos didinimo būdai, sukurtas naujas laikinio skaitmeninio keitiklio modelis. Siūloma dažnio sintezatoriaus struktūra daugiajuosčiams siųs- tuvams-imtuvams. Trečiajame skyriuje pagal iškeltus reikalavimus daugiajuosčio dažnio sinte- zatoriaus blokams, taikant kompiuterinių skaičiavimų ir eksperimentinius meto- dus yra kuriami ir tiriami laikinio skaitmeninio keitiklio, skaitmeniniu būdu val- domo generatoriaus bei skaitmeninio filtro integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 4 – mokslo žurna- luose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 1 – tarp- tautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analytics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duo- menų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti devyniose mokslinėse konferencijose Lietuvoje ir užsienyje

A 2.4 GHz Phase Modulator for a WLAN OFDM Polar Transmitter in 0.18 um CMOS

This research focuses on the design and implementation of a digital active phase modulator path of a polar transmitter in the case of orthogonal frequency division multiplex WLAN application. The phase modulation path of the polar transmitter provides a constant envelope phase modulated signal to the Power amplifier(PA) , operating in nonlinear high efficient switching mode. The core design of the phase modulator is based on linear vector-sum phase shifting topology to differential quadrature input signals. The active phase shifter consists of a DAC that generates binary weighted currents for I and Q branches and differential signed adder that vector-sums the generated quadrature currents to generate the phase at the output.6 bits control the phase shifter, creating 64 states with the resolution of 5:625° for the whole 360°. The linear (binary weighted) vector-sum technique generates a reduction in the resultant amplitude that should be taken into consideration in case of nonlinear PA in polar transmission. On the other hand, the digital phase information is applied as the control bits to the phase shifter that determine the weightings and the signs of the I and Q vectors. The key point is the operation of the phase modulator in terms of phase accuracy, with the wideband modulation standard such as OFDM WLAN. A technique has been proposed to enable the polar phase modulator to operate with a real-time wideband data and to compensate for the phase shifter output reduction. Since the reduction in gain is due to vector sum resultant of I and Q currents, it is compensated by modifying the I and Q currents for each 64 phase states. The design is implemented using 0.18 um CMOS technology and measured with maximum data rate of 64 QAM,OFDM modulation of WLAN standard. The output amplitude of the phase shifter with the correction technique is approximately constant over the 64 states with maximum variation of 3.5mv from the constant peak to peak value. The maximum achieved phase error is about 2° with a maximum DNL of 0.257

A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration

The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry\u27s characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc. This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis

Hybrid DDS-PLL based reconfigurable oscillators with high spectral purity for cognitive radio

Analytical, design and simulation studies on the performance optimization of reconfigurable architecture of a Hybrid DDS – PLL are presented in this thesis. The original contributions of this thesis are aimed towards the DDS, the dithering (spur suppression) scheme and the PLL. A new design of Taylor series-based DDS that reduces the dynamic power and number of multipliers is a significant contribution of this thesis. This thesis compares dynamic power and SFDR achieved in the design of varieties of DDS such as Quartic, Cubic, Linear and LHSC. This thesis proposes two novel schemes namely “Hartley Image Suppression” and “Adaptive Sinusoidal Interference Cancellation” overcoming the low noise floor of traditional dithering schemes. The simulation studies on a Taylor series-based DDS reveal an improvement in SFDR from 74 dB to 114 dB by using Least Mean Squares -Sinusoidal Interference Canceller (LM-SIC) with the noise floor maintained at -200 dB. Analytical formulations have been developed for a second order PLL to relate the phase noise to settling time and Phase Margin (PM) as well as to relate jitter variance and PM. New expressions relating phase noise to PM and lock time to PM are derived. This thesis derives the analytical relationship between the roots of the characteristic equation of a third order PLL and its performance metrics like PM, Gardner’s stability factor, jitter variance, spur gain and ratio of noise power to carrier power. This thesis presents an analysis to relate spur gain and capacitance ratio of a third order PLL. This thesis presents an analytical relationship between the lock time and the roots of its characteristic equation of a third order PLL. Through Vieta’s circle and Vieta’s angle, the performance metrics of a third order PLL are related to the real roots of its characteristic equation