Resonation-based hybrid continuous-time/discrete-time cascade ΣΔ modulators: application to 4G wireless telecom

This paper presents innovative architectures of hybrid Continuous-Time/Discrete-Time (CT/DT) cascade ΣΔ Modulators (ΣΔMs) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth as compared to conventional ΣΔMs, the proposed topologies take advantage of the CT nature of the front-end ΣΔM stage, by embedding anti-aliasing filtering as well as their suitability to operate up to the GHz range. Moreover, the presented modulators include multi-bit quantization and Unity Signal Transfer Function (USTF) in both stages to reduce the integrator output swings, and programmable resonation to optimally distribute the zeroes of the overall Noise Transfer Function (NTF), such that the in-band quantization noise is minimized for each operation mode. Both local and inter-stage (global) based resonation architectures are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit non-ideal effects. The combination of all mentioned characteristics results in novel hybrid ΣΔMs, very suited for the implementation of adaptive/reconfigurable Analog-to-Digital Converters (ADCs) intended for the 4th Generation (4G) of wireless telecom systems

Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits

This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs). Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB. The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date

A survey on continuous-time modulators : theory, designs and implementations

Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm

Accurate Time-Domain Simulation of Continuous-Time Sigma–Delta Modulators

International audienceIn this paper we present a methodology for the simulation of continuous-time sigma-delta converters. This method, based on a fixed-step algorithm, permits not only a time-domain simulation of the modulator output but also the simulation of intermediary signals. The method is based on the discretization of the continuous-time models and the use of a discrete simulator such as Simulink, which is more efficient than an analog simulator. By using filters with a sampling frequency higher than the modulator output frequency, the model can simulate input signals with a bandwidth which is higher than half the modulator sampling frequency. The transformation is exact in terms of Noise Transfer Function and asymptotically exact in terms of Signal Transfer Function (the Transfer Function from the modulator input to each stage filter output rapidly tends to the continuous-time model transfer function when the number of steps increases)

A SigmaDelta modulator for digital hearing instruments using 0.18 mum CMOS technology.

This thesis develops the design methodology for a low-voltage low-power SigmaDelta Modulator, realized using a switched op-amp technique that can be used in a hearing instrument. Switched op-amp implementation allows scaling down the design to the latest CMOS technology. A single-loop second-order SigmaDelta Modulator topology is chosen. The modulator circuit features reduced complexity, area reduction and low conversion energy. The modulator has a sampling rate of 8.2 MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16 kHz. The modulator is implemented in a 0.18 mum digital CMOS technology with metal-to-metal sandwich structure capacitors. The modulator operates with a supply voltage of 1.8 V. The active area is 0.403 mm2. The modulator achieves a 98 dB signal-to-noise-and-distortion ratio (SNDR) and a 100 dB dynamic range (DR) at a Nyquist conversion rate of 32 kHz and consumes 1321 muW with a joule/conversion figure of merit equal to 161 x 10-12 J/s. The design methodology is developed through the extensive use of simulation tools. The behaviour simulation is carried out using Matlab/SIMULINK while circuits are simulated with Hspice using the Cadence design tools. Full-custom layout for the analog and the digital circuits is performed using the Cadence design tool. Post-processing simulation of the extracted modulator with parasitic verifies that results meet the requirements. The design has been sent to CMC for fabrication. Source: Masters Abstracts International, Volume: 43-03, page: 0947. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

A Continuous-Time Delta-Sigma Modulator for Ultra-Low-Power Radios

The increasing need of digital signal processing for telecommunication and multimedia applications, implemented in complementary metal-oxide semiconductor (CMOS) technology, creates the necessity for high-resolution analog-to-digital converters (ADCs). Based on the sampling frequency, ADCs are of two types: Nyquist-rate converters and oversampling converters. Oversampling converters are preferred for low-bandwidth applications such as audio and instrumentation because they provide inherently high resolution when coupled with proper noise shaping. This allows to push noise out of signal band, thus increasing the signal-to-noise ratio (SNR). Continuous time delta-sigma ADCs are becoming more popular than discrete-time ADCs primarily because of inherent anti-aliasing filtering, reduced settling time and low-power consumption. In this thesis, a 2nd-order 4-bits continuous-time (CT) delta-sigma modulator (DSM) for radio applications is designed. It employs a 2nd-order loop filter with a single operational amplifier. Implemented in a 65-nanometer CMOS technology, the modulator runs on a 0.8-V supply and achieves a SNR of 70dB over a 500-kHz signal bandwidth. The modulator operates with an oversampling ratio (OSR) of 16 and a sampling frequency of 16MHz. In the first chapter the principles of ΔΣ modulators are analysed, introducing the differences between discrete-time (DT) modulators and continuous-time (CT) modulators. In the next chapter the techniques to design a ΔΣ modulators for ultra-low-power radios are presented. The third chapter talks over the design of the operational amplifier, which appears inside the loop filter. In the fourth chapter the performance of the complete ΔΣ modulator, which employs a flash quantizer, is shown. Finally, in the last chapter, a performance analysis is carried out replacing the flash quantizer with an asynchronous SAR quantizer. The analysis shows that a further reduction of the quantizer power consumption of about 40% is possible. The conjunction of this replacement with the power-saving technique implemented in the loop filter appears relevant

Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes

The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies. For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8μW and occupies an area of 5.4 µm x 610 µm. For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ΔΣM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ΔΣM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)

The design of a 250MHz CMOS bandpass sigma-delta A/D modulator with continuous-time circuitry

Master'sMASTER OF ENGINEERIN

LOW-VOLTAGE LOW-POWER ANALOG-TO-DIGITAL CONVERTERS

Ph.DDOCTOR OF PHILOSOPH