On-die transient event sensors and system-level ESD testing

System level electrostatic discharge (ESD) testing of electronic products is a critical part of product certification. Test methods were investigated to develop system level ESD simulation models to predict soft-failures in a system with multiple sensors. These methods rely completely on measurements. The model developed was valid only for the linear operation range of devices within the system. These methods were applied to a commercial product and used to rapidly determine when a soft failure would occur. Attaching cables and probes to determine stress voltages and currents within a system, as in the previous study, is time-consuming and can alter the test results. On-chip sensors have been developed which allow the user to avoid using cables and probes and can detect an event along with the level, polarity, and location of a transient event seen at the I/O pad. The sensors were implemented with minimum area consumption and can be implemented within the spacer cell of an I/O pad. Some of the proposed sensors were implemented in a commercial test microcontroller and have been tested to successfully record the event occurrence, location, level, and polarity on that test microcontroller. System level tests were then performed on a pseudo-wearable device using the on-chip sensors. The measurements were successful in capturing the peak disturbance and counting the number of ESD events without the addition of any external measurement equipment. A modification of the sensors was also designed to measure the peak voltage on a trace or pin inside a complex electronic product. The peak current can also be found when the sensor is placed across a transient voltage suppressor with a known I-V curve. The peak level is transmitted wirelessly to a receiver outside the system using frequency-modulated magnetic or electric fields, thus allowing multiple measurements to be made without opening the enclosure or otherwise modifying the system. Simulations demonstrate the sensors can accurately detect the peak transient voltage and transmit the level to an external receiver --Abstract, page iv

Optimization of ESD Protection Methods in Electronics Assembly Based on Process and Product Specific Risks

The last 40 years has seen significant development in electrical component and system technologies. However, advances with semiconductor technologies, cost optimizations, and die area shrinking have made electronics more sensitive to excess electrical stress and electromagnetic disturbances. In this dissertation work, one of these stress scenarios is studied: electrostatic discharge (ESD) risks in the electronics assembly process environment. In the assembly process, single electrical components, circuit boards, and different subassemblies are assembled together, tested, and programmed to complete fully functional electrical products.A noncontrolled electronics assembly environment produces unpredictable ESD risks and causes yield losses. Therefore, it is necessary to protect electronics against ESD during handling and manufacturing. This is accomplished with the aid of an electrostatic protected area (EPA) and an ESD control program plan, which are typically built according to IEC61340-5-1-2007 and ANSI S20.20-2014 standards. These two standards define how to design, establish, implement, and maintain the program with administrative and technical requirements. Here, a 100 V human body model (HBM) limit is currently used as the base for building EPAs and ESD control programs. However, current ESD control programs are not always able to prevent ESD damages in EPA. On top of actual ESD events, there can be electromagnetic interference (EMI) initiated product and equipment disturbances in well-built EPAs.In this research work, the main focus is on additional ESD control methods that go beyond the specifications and requirements of the IEC61340-5-1 and ANSI/ESD S20.20 standards. The objective is to optimize ESD protection methods based on real ESD risk scenarios found during PCB assembly, testing, handling, and during system final assembly to achieve close to zero-failure level. At the same time, the objective is to optimize ESD control-related costs in the process area.Based on the research, the focus of the additional ESD and EMI control methods should be with final assembly, programming, and testing process phases where about 90% observed failure and disturbance cases have occurred. Therefore, in an improved ESD control program, EMI control, controlling product part and cable charging are added into the program, together with groundings and other basic controlled EPA items. The charging of product parts should be monitored with potential, discharge current and charge meters, and that data should be used together with process analysis to detect all known ESD risk scenarios. The sensitivity of subassemblies should be tested, for example, by using a charged board event (CBE), field collapse event (FCE), and cable discharge event (CDE) methods that simulate real world ESD scenarios found in the process area. This gives more accurate data for risk assessments than an electrical-component-specific HBM or charged device model (CDM) qualification data.The proposed additional control methods were implemented in more than 10 large electronics assembly facilities, resulting in a significant reduction in ESD-related failures and disturbance-related process yield challenges. Therefore, as a future work, product and process specific ESD and EMI risk should be emphasized in ESDcontrol-related trainings, standards, standard practices, and technical reports

Etude de la robustesse d'amplificateurs embarqués dans des applications portables soumis à des décharges électrostatiques (ESD) au niveau système

Avec les évolutions technologiques, les composants électroniques deviennent de plus en plus sensibles aux décharges électrostatiques (ESD). De nos jours, la fiabilité des circuits intégrés dans les étapes de fabrication est garantie par un ensemble de normes définissant des niveaux de robustesse. Mais les stratégies de protection implémentées dans les circuits intégrés, visant à respecter ces normes, ne suffisent pas toujours à garantir la robustesse des composants dans leur application finale. Ces nouveaux problèmes de fiabilité ne sont pas encore bien compris, étant donnée la complexité des phénomènes mis en jeu dans un système réel en fonctionnement. En tenant compte de ces faits, nous pouvons nous interroger sur l'efficacité des stratégies de protection contre les ESD utilisées de façon conventionnelle pour protéger contre des stress de type système. L'ensemble des travaux de thèse présentés vise à l'amélioration de la robustesse, quant à ces nouvelles exigences, de composants analogiques dédiés aux applications portables (téléphonie, multimédia). En partant d'un cas concret, pour lequel il existe une grande différence de robustesse entre le produit alimenté et non-alimenté, nous présenterons les différents résultats d'analyse (analyse de défaillance, caractérisation électrique en impulsion de type TLP et VFTLP, simulations de type SPICE) qui nous ont conduits à proposer une solution de protection intégrée respectant les exigencesWith improvement in electronic technology shrinking, electronic components are increasingly becoming sensitive to ElectroStatic Discharge (ESD). Nowadays, the reliability of integrated circuits in the manufacturing field are guaranteed by a set of standards that define levels of robustness. Nevertheless the protection strategies implemented in integrated circuits, designed to meet these standards, are not always enough to ensure the robustness of the components in their final application. The new reliability problems are not well understood, given the complexity of the phenomena involved in real systems in operation. Taking into account these facts, we can question the effectiveness of the strategies used to protect against " classical ESD " and system-type stresses. All the work presented in this thesis aims to improve the robustness with respect to these new requirements, in the case study of analog components dedicated to portable applications (telephony, multimedia). Starting from a concrete case, for which there is a large difference in the system ESD robustness between the biased and unbiased product, we will present the various results of analysis (failure analysis, electrical characterization by impulse like TLP VFTLP, SPICE-type simulations) that led us to the proposal of an integrated security solution that meets the requirement

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

NASA Tech Briefs, February 2001

The topics include: 1) Application Briefs; 2) National Design Engineering Show Preview; 3) Marketing Inventions to Increase Income; 4) A Personal-Computer-Based Physiological Training System; 5) Reconfigurable Arrays of Transistors for Evolvable Hardware; 6) Active Tactile Display Device for Reading by a Blind Person; 7) Program Automates Management of IBM VM Computer Systems; 8) System for Monitoring the Environment of a Spacecraft Launch; 9) Measurement of Stresses and Strains in Muscles and Tendons; 10) Optical Measurement of Temperatures in Muscles and Tendons; 11) Small Low-Temperature Thermometer With Nanokelvin Resolution; 12) Heterodyne Interferometer With Phase-Modulated Carrier; 13) Rechargeable Batteries Based on Intercalation in Graphite; 14) Signal Processor for Doppler Measurements in Icing Research; 15) Model Optimizes Drying of Wet Sheets; 16) High-Performance POSS-Modified Polymeric Composites; 17) Model Simulates Semi-Solid Material Processing; 18) Modular Cryogenic Insulation; 19) Passive Venting for Alleviating Helicopter Tail-Boom Loads; 20) Computer Program Predicts Rocket Noise; 21) Process for Polishing Bare Aluminum to High Optical Quality; 22) External Adhesive Pressure-Wall Patch; 23) Java Implementation of Information-Sharing Protocol; 24) Electronic Bulletin Board Publishes Schedules in Real Time; 25) Apparatus Would Extract Water From the Martian Atmosphere; 26) Review of Research on Supercritical vs Subcritical Fluids; 27) Hybrid Regenerative Water-Recycling System; 28) Study of Fusion-Driven Plasma Thruster With Magnetic Nozzle; 29) Liquid/Vapor-Hydrazine Thruster Would Produce Small Impulses; and 30) Thruster Based on Sublimation of Solid Hydrazin

Robustness of monochromatic LED modules towards electrostatic discharge events

In this work the robustness of LEDs and LED modules towards ESDs was investigated. A TLP system was used to generate negative-bias ESD pulses. Three different types of LEDs (green, blue and red) were tested, both singularly (with and without the use of an EMCCD camera to detect light emission) and in monochromatic modules. An analysis of the type of failure of the single LEDs was also carried out. The results showed that that different types of devices (and modules) have a different behaviour

Design and fabrication of ion traps for a scalable microwave quantum computer

This thesis describes the experimental work towards the development of a scalable quantum computer based on microfabricated ion trap using long-wavelength radiation and magnetic field gradient. There are three key elements in implementing such a quantum computer: the junction trap to shuttle ions, the structure to generate high gradient magnetic field and the structure to induce strong microwave coupling to the ions. A new dynamic simulation tool was developed addressing the problems faced by static solvers. This tool was used to aid the design and optimisation of an X junction geometry allowing the ions to be shuttled with minimised motional heating gain. The design and fabrication techniques were reported on the structure to generate a high gradient magnetic field. A discussion was given on the design of producing microwave and maximise the coupling to the cold ions. A review was given on the far-field methods and near-field methods. A novel design was reported where the single-qubit gate is predicted to be 45 times faster than a conventional setup. Two essential topics on the microfabrication of a reliable scalable quantum computer unit were discussed: breakdown and RF loss. Investigation using numerical simulations showed that dielectric can breakdown due to high voltage and local heating which are results of impedance mismatch. Microfabrication processes were improved, high-quality films were reported to have twice as much breakdown voltages. The mechanisms of RF loss were reviewed. Novel structures and smooth electroplating technique were developed to minimise the loss. A low loss ion trap was produced and tested. An experimentally observed anomalous glow discharge phenomenon was reported and investigated

An investigation into computer and network curricula

This thesis consists of a series of internationally published, peer reviewed, journal and conference research papers that analyse the educational and training needs of undergraduate Information Technology (IT) students within the area of Computer and Network Technology (CNT) Education. Research by Maj et al has found that accredited computing science curricula can fail to meet the expectations of employers in the field of CNT: “It was found that none of these students could perform first line maintenance on a Personal Computer (PC) to a professional standard with due regard to safety, both to themselves and the equipment. Neither could they install communication cards, cables and network operating system or manage a population of networked PCs to an acceptable commercial standard without further extensive training. It is noteworthy that none of the students interviewed had ever opened a PC. It is significant that all those interviewed for this study had successfully completed all the units on computer architecture and communication engineering (Maj, Robbins, Shaw, & Duley, 1998). The students\u27 curricula at that time lacked units in which they gained hands-on experience in modern PC hardware or networking skills. This was despite the fact that their computing science course was level one accredited, the highest accreditation level offered by the Australian Computer Society (ACS). The results of the initial survey in Western Australia led to the introduction of two new units within the Computing Science Degree at Edith Cowan University (ECU), Computer Installation & Maintenance (CIM) and Network Installation & Maintenance (NIM) (Maj, Fetherston, Charlesworth, & Robbins, 1998). Uniquely within an Australian university context these new syllabi require students to work on real equipment. Such experience excludes digital circuit investigation, which is still a recommended approach by the Association for Computing Machinery (ACM) for computer architecture units (ACM, 2001, p.97). Instead, the CIM unit employs a top-down approach based initially upon students\u27 everyday experiences, which is more in accordance with constructivist educational theory and practice. These papers propose an alternate model of IT education that helps to accommodate the educational and vocational needs of IT students in the context of continual rapid changes and developments in technology. The ACM have recognised the need for variation noting that: There are many effective ways to organize a curriculum even for a particular set of goals and objectives (Tucker et al., 1991, p.70). A possible major contribution to new knowledge of these papers relates to how high level abstract bandwidth (B-Node) models may contribute to the understanding of why and how computer and networking technology systems have developed over time. Because these models are de-coupled from the underlying technology, which is subject to rapid change, these models may help to future-proof student knowledge and understanding of the ongoing and future development of computer and networking systems. The de-coupling is achieved through abstraction based upon bandwidth or throughput rather than the specific implementation of the underlying technologies. One of the underlying problems is that computing systems tend to change faster than the ability of most educational institutions to respond. Abstraction and the use of B-Node models could help educational models to more quickly respond to changes in the field, and can also help to introduce an element of future-proofing in the education of IT students. The importance of abstraction has been noted by the ACM who state that: Levels of Abstraction: the nature and use of abstraction in computing; the use of abstraction in managing complexity, structuring systems, hiding details, and capturing recurring patterns; the ability to represent an entity or system by abstractions having different levels of detail and specificity (ACM, 1991b). Bloom et al note the importance of abstraction, listing under a heading of: “Knowledge of the universals and abstractions in a field” the objective: Knowledge of the major schemes and patterns by which phenomena and ideas arc organized. These are large structures, theories, and generalizations which dominate a subject or field or problems. These are the highest levels of abstraction and complexity\u27\u27 (Bloom, Engelhart, Furst, Hill, & Krathwohl, 1956, p. 203). Abstractions can be applied to computer and networking technology to help provide students with common fundamental concepts regardless of the particular underlying technological implementation to help avoid the rapid redundancy of a detailed knowledge of modem computer and networking technology implementation and hands-on skills acquisition. Again the ACM note that: “Enduring computing concepts include ideas that transcend any specific vendor, package or skill set... While skills are fleeting, fundamental concepts are enduring and provide long lasting benefits to students, critically important in a rapidly changing discipline (ACM, 2001, p.70) These abstractions can also be reinforced by experiential learning to commercial practices. In this context, the other possibly major contribution of new knowledge provided by this thesis is an efficient, scalable and flexible model for assessing hands-on skills and understanding of IT students. This is a form of Competency-Based Assessment (CBA), which has been successfully tested as part of this research and subsequently implemented at ECU. This is the first time within this field that this specific type of research has been undertaken within the university sector within Australia. Hands-on experience and understanding can become outdated hence the need for future proofing provided via B-Nodes models. The three major research questions of this study are: •Is it possible to develop a new, high level abstraction model for use in CNT education? •Is it possible to have CNT curricula that are more directly relevant to both student and employer expectations without suffering from rapid obsolescence? •Can WI effective, efficient and meaningful assessment be undertaken to test students\u27 hands-on skills and understandings? The ACM Special Interest Group on Data Communication (SJGCOMM) workshop report on Computer Networking, Curriculum Designs and Educational Challenges, note a list of teaching approaches: ... the more \u27hands-on\u27 laboratory approach versus the more traditional in-class lecture-based approach; the bottom-up approach towards subject matter verus the top-down approach (Kurose, Leibeherr, Ostermann, & Ott-Boisseau, 2002, para 1). Bandwidth considerations are approached from the PC hardware level and at each of the seven layers of the International Standards Organisation (ISO) Open Systems Interconnection (OSI) reference model. It is believed that this research is of significance to computing education. However, further research is needed

Journal of Microelectronic Research - May 2003

https://scholarworks.rit.edu/meec_archive/1012/thumbnail.jp

Contribution to the development of pico-satellites for Earth observation and technology demonstrators

The submitted Ph.D. thesis is a contribution to the development of pico-satellites and nano-satellites for Earth Observation and Technology Demonstrators. Development of satellites with a mass from 1 kg up to 10 kg has really boosted during the past 15 years offering large costs reduction with respect to conventional (larger) satellites at compromised performances. However, these performances are increasing step by step, and their potential is about to explode. With 1.3 kg and a volume of 1 liter, 3Cat-1 is the first pico-satellite class satellite with up to seven different payloads on board: a harvesting energy powered beacon, a new topology solar cells, an optical sensor, a Geiger counter, a mono-atomic MEMS oxygen detector, a graphene transistor, and a Wireless Power Transfer experiment. Additionally, many main subsystems like the Electrical Power, the Attitude Determination and Control, and the Communication subsystems have been developed during this PhD. A description of each subsystem and how they have been integrated under these constrains are described in this PhD Thesis report. In the subsystems and in the experiments there are novel concepts and designs that will be explained. Some have been already published in the technical and scientific literature, others will be in the near future.Tesi doctoral és una contribució al desenvolupament de pico-satèl.lits per a observació de la Terra i demostradors tecnològics. El desenvolupament de satèl¿lits amb massa d'entre 1 kg i 10 kg ha crescut ràpidament durant els darrers 15 anys, oferint importants reduccions de cost respecte els satèl.lits més convencionals (i més grans) amb unes prestacions menors però al mateix temps, acceptables. No obstant, aquestes prestacions estan millorant pas a pas, i el seu potencial a prop d'explosionar. Amb una massa de 1.3 kg i un volum d'un litre, el 3Cat-1 és el primer pico-satèl.lit de la seva categoria equipat amb set diferents càrregues útils a bord: un senyal de radio-balisa alimentat amb energia provinent d'un sistema recol.lector d'energia ambient, una nova topologia de cel.les solars, un sensor òptic, un comptador Geiger, un detector MEMS d'oxigen atòmic, un transistor de grafè, i un experiment de transmissió d'energia per acoblament inductiu. A més a més, molts dels subsistemes com ara el d'energia elèctrica, control i determinació d'actitud, i el subsistema de comunicacions han estat desenvolupats durant aquesta Tesi doctoral. Una descripció de cada subsistema, i com han estat integrats en condicions d'espai, massa i energia reduïdes, s'explica en aquest document. En els subsistemes i en els experiments hi ha nous conceptes i dissenys explicats. Alguns han estat ja publicats en la literatura científica mentre que altres ho seran en un futur prope