Model Development and Assessment of the Gate Network in a High-Performance SiC Power Module

The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to offer remedies to these issues to increase the overall performance, robustness, and reliability of the technology. In order to accomplish this goal, a highly accurate model of the gate network is developed through three methods of parameter extraction: calculation, simulation, and measurement. A SPICE model of the gate network is developed to analyze four electrical issues in a high-speed, SiC-based power module including the necessary internal gate resistance for damping under-voltage and over-voltage transients, the disparity in switching loss between paralleled devices due to propagation delay, a high-frequency oscillatory behavior on gate voltage due to die-to-die interactions, and current equalization in the kelvin-source signal path. In addition, the analysis of parameter variance between paralleled MOSFETs and the effects of mismatched threshold voltage and on-state resistance on switching loss and junction temperature are investigated. Finally, three Miller Clamp topologies are simulated and assessed for effectiveness culminating in a solution for parasitic turn-on in high dv/dt systems such as those utilizing high-performance SiC power modules

Gate Drive Design for Paralleled SiC MOSFETs in High Power Voltage Source Converters

High power voltage source converters (VSC) are vital in applications ranging from industrial motor drives to renewable energy systems and electrified transportation. In order to achieve high power the semiconductor devices used in a VSC need to be paralleled, making the gate drive design complicated. The silicon carbide (SiC) MOSFET brings much benefit over similarly rated silicon (Si) devices but further complicates the gate drive design in a parallel environment due to it’s fast switching capability and limited short-circuit withstand time. A gate driver design with proper accommodation of key issues for paralleled 1.7 kV SiC MOSFETs in high power VSC applications is developed.Three of the main issues are current imbalance, short-circuit protection, and cross-talk. By characterizing devices and supporting circuitry an understanding of constraints and sensitivities with regards to current balance between devices is developed for design optimization. A short-circuit detection scheme with adequate response time is employed and mitigation steps presented for issues arising from paralleling devices including large transient energy and instability. Cdv/dt induced gate voltage—cross-talk—is addressed by adapting a mitigation method to multiple devices. Finally, the gate driver is demonstrated in a full scale half-bridge using four devices per switch

Active gate drivers for high-frequency application of SiC MOSFETs

The trend in the development of power converters is focused on efficient systems with high power density, reliability and low cost. The challenges to cover the new power converters requirements are mainly concentered on the use of new switching-device technologies such as silicon carbide MOSFETs (SiC). SiC MOSFETs have better characteristics than their silicon counterparts; they have low conduction resistance, can work at higher switching speeds and can operate at higher temperature and voltage levels. Despite the advantages of SiC transistors, operating at high switching frequencies, with these devices, reveal new challenges. The fast switching speeds of SiC MOSFETs can cause over-voltages and over-currents that lead to electromagnetic interference (EMI) problems. For this reason, gate drivers (GD) development is a fundamental stage in SiC MOSFETs circuitry design. The reduction of the problems at high switching frequencies, thus increasing their performance, will allow to take advantage of these devices and achieve more efficient and high power density systems. This Thesis consists of a study, design and development of active gate drivers (AGDs) aimed to improve the switching performance of SiC MOSFETs applied to high-frequency power converters. Every developed stage regarding the GDs is validated through tests and experimental studies. In addition, the developed GDs are applied to converters for wireless charging systems of electric vehicle batteries. The results show the effectiveness of the proposed GDs and their viability in power converters based on SiC MOSFET devices.La tendencia en el diseño y desarrollo de convertidores de potencia está enfocada en realizar sistemas eficientes con alta densidad de potencia, fiabilidad y bajo costo. Los retos para cubrir esta tendencia están centrados principalmente en el uso de nuevas tecnologías de dispositivos de conmutación tales como, MOSFETs de carburo de silicio (SiC). Los MOSFETs de SiC presentan mejores características que sus homólogos de silicio; tienen baja resistencia de conducción, pueden trabajar a mayores velocidades de conmutación y pueden operar a mayores niveles de temperatura y tensión. A pesar de las ventajas de los transistores de SiC, existen problemas que se manifiestan cuando estos dispositivos operan a altas frecuencias de conmutación. Las rápidas velocidades de conmutación de los MOSFETs de SiC pueden provocar sobre-voltajes y sobre-corrientes que conllevan a problemas de interferencia electromagnética (EMI). Por tal motivo, el desarrollo de controladores de puertas es una etapa fundamental en los MOSFETs de SiC para eliminar los problemas a altas frecuencias de conmutación y aumentar su rendimiento. En consecuencia, aprovechar las ventajas de estos dispositivos y lograr sistemas más eficientes y con alta densidad de potencia. En esta tesis, se realiza un estudio, diseño y desarrollo de controladores activos de puerta para mejorar el rendimiento de conmutación de los MOSFETs de SiC aplicados a convertidores de potencia de alta frecuencia. Los controladores son validados a través de pruebas y estudios experimentales. Además, los controladores de puerta desarrollados son aplicados en convertidores para sistemas de carga inalámbrica de baterías de vehículos eléctricos. Los resultados muestran la importancia de los controladores de compuerta propuestos y su viabilidad en convertidores de potencia basados en carburo de silicio

Design Considerations for Paralleling Multiple Chips in SiC Power Modules

With the benefits of fast switching speed, low on-resistance and high thermal conductivity, silicon carbide (SiC) devices are being implemented in converter designs with high efficiency and high power density. Consequently, SiC power modules are needed. However, some of the preestablished package designs for silicon based power modules are not suitable to manifest the advantages of SiC devices. Therefore, this thesis aims at optimizing the package design to utilize the fast switching capability of SiC devices. First, the power loop parasitic inductance induced by the package can lead to large voltage spikes with the fast switching SiC device. It can potentially exceed the device’s voltage ratings and affect its safe operation. Second, to achieve high power density design with SiC devices, the package’s cooling performance needs to be improved. Third, to design a package for high current applications with multiple chips in parallel, a proper scaling method is needed to ensure all the devices undertake the same voltage stress in switching transients. For P-cell/N-cell designs with split scaling, a new parasitic parameter, namely, middle-point parasitic inductance Lmiddle will be introduced. Its role should be understood. Lastly, the unbalanced dynamic switching loss can lead to different state junction temperatures among paralleled devices. Thermal coupling can help to reduce the temperature imbalance, and its role should be quantitatively investigated. To meet the first two requirements, a new package design is proposed with reduced parasitic inductance and double-sided cooling. Compared to a baseline package, more than 60% reduction of parasitic inductance is achieved. The middle-point parasitic inductance’s effect on device’s switching transients is analyzed in the frequency domain. Then a dedicated power module is fabricated with the capability of varying Lmiddle. Experiment results show that as Lmiddle increases, different voltage stresses are imposed on the MOSFET and anti-parallel diode. Electrothermal simulations are implemented to investigate steady state junction temperatures of paralleled devices considering unbalanced switching losses at different thermal coupling conditions. It is observed that both devices’ junction temperatures will increase as the coupling coefficient is increased. However, the junction temperature imbalance will decrease. This is verified by the experiment result

An investigation of temperature sensitive electrical parameters for SiC power MOSFETs

This paper examines dynamic Temperature Sensitive Electrical Parameters (TSEPs) for SiC MOSFETs. It is shown that the output current switching rate (dIDS/dt) coupled with the gate current plateau (IGP) during turn-ON would be the most effective under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dIDS/dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance (RGEXT). However, as dIDS/dt is increased by using a small RGEXT, parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dIDS/dt is at the highest with maximum RGEXT, there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as well as the compromise between the increased switching loss and the potential to implement effective condition monitoring using the evaluated TSEPs

Switching Performance Evaluation, Design, and Test of a Robust 10 kV SiC MOSFET Based Phase Leg for Modular Medium Voltage Converters

10 kV SiC MOSFETs are one of the most promising power semiconductor devices for next-generation high-performance modular medium voltage (MV) converters. With extraordinary device characteristics, 10 kV SiC MOSFETs also bring a variety of challenges in the design and test of MV converters. To tackle these inherent challenges, this dissertation focuses on a robust half bridge (HB) phase leg based on 10 kV SiC MOSFETs for modular MV converters. A baseline design and test of the phase leg is established first as the foundation of the research in this dissertation. Thorough evaluation of 10 kV SiC MOSFETs’ switching performance in a phase leg is necessary before applying them in MV converters. The impact of parasitic capacitors and the freewheeling diode is investigated to understand the switching performance more extensively and guide the converter design. One non-negligible challenge is the flashover fault resulting from the premature insulation breakdown, a short circuit fault with extremely fast transients. A device model is established to analyze the behavior of 10 kV SiC MOSFETs when the fault occurs in a phase leg thoroughly. Subsequently, the gate driver and protection design considerations are summarized to achieve lower short circuit current and overvoltage and ensure the survival of the MOSFET that in ON state when the fault happens. Furthermore, it is challenging to design the overcurrent/short circuit protection with fast response and strong noise immunity under fast switching transients for 10 kV SiC MOSFETs. The noise immunity of the desaturation (desat) protection is studied quantitatively to provide design guidelines for noise immunity enhancement. Then, the protection scheme based on desat protection is developed and validated withimmunity, the strong noise immunity of the developed protection is also successfully validated. In addition, a simple test scheme is proposed and validated experimentally, in order to qualify the HB phase leg based on the 10 kV SiC MOSFET comprehensively for the modular MV converter applications. The test scheme includes the ac-dc continuous test with two phase legs in series to create the testing condition similar to what is generated in a modular MV converter, especially the high dv/dt. The test scheme can fully test the capability of the phase leg to withstand high dv/dt and its resulting noise

Methodology to Improve Switching Speed of SiC MOSFETs in Hard Switching Applications

To meet the higher efficiency and power density requirement for power converters, the switching speed of power devices is preferred to increase. Thanks to silicon carbide (SiC) power MOSFETs, their intrinsic superior switching characteristics compared with silicon IGBTs makes it possible to run converters at faster switching speed in hard switching applications. Nevertheless, the switching speed is not only dependent on the device’s characteristics, but also strongly related to the circuit like gate drive and parasitics. To fully utilize the potential of SiC MOSFETs, the impact factors limiting the switching speed are required to be understood. Specific solutions and methods need to be developed to mitigate the influence from these impact factors.The characterization of the switching speed for SiC MOSFETs with different current ratings is conducted with double pulse test (DPT) first. Based on the result, the impact factors of switching speed are evaluated in detail.According to the evaluation, the switching speed of SiC discrete devices with low current rating is mainly limited by the gate drive capability. A current source gate drive as well as a charge pump gate drive are proposed, which can provide higher current during the switching transient regardless of the low transconductance and large internal gate resistance of SiC discrete devices.For SiC power modules with high current rating, the switching speed is mainly determined by the device drain-source overvoltage resulting from circuit parasitics. An analytical model for the multiple switching loops related overvoltage in 3L-ANPC converters is established. A simple modulation is developed to mitigate the effect of the non-linear device output capacitance, which helps reduce the overvoltage and enables higher switching speed operation of SiC power modules.Furthermore, the layout design methodology for three-level converters concerning the multiple commutation loops is introduced. The development of a laminated busbar for a 500 kVA 3L-ANPC converter with SiC power modules is presented in detail.Finally, a SiC based 1 MW inverter is built and tested to operate at cryogenic temperature. The proposed control and busbar above are utilized to increase the switching speed of the SiC power module

Design and measurement considerations for WBG switching circuits

Wide Band Gap (WBG) transistors using materials such as Gallium Nitride (GaN) and Silicon Carbide (SiC) offer superior electrical and thermal properties, as well as fast switching capability. However, the high dv/dt and high di/dt may cause ringing with the parasitic inductances and capacitances in the switching loop, increasing overshoot voltages and reducing confidence in the design. Also, making accurate measurements of the switching behaviour without unduly loading the circuit under test is challenging and further impedes the development of WBG applications. This paper presents a prototype WBG Development Platform, built around a half-bridge switched inductive load test circuit. Additional circuits are integrated on to the main PCB for test and measurement purposes: These include a high bandwidth linear current gate-drive circuit and a high bandwidth on-board measurement system. These sub-circuits are described in detail in this paper, together with the switching waveforms that have been achieved during tests with SiC MOSFETs. The authors demonstrate a practical implementation for high frequency WBG power circuits