The main objective of this effort is to determine points of weakness in the gate network of a high-performance SiC power module and to offer remedies to these issues to increase the overall performance, robustness, and reliability of the technology. In order to accomplish this goal, a highly accurate model of the gate network is developed through three methods of parameter extraction: calculation, simulation, and measurement. A SPICE model of the gate network is developed to analyze four electrical issues in a high-speed, SiC-based power module including the necessary internal gate resistance for damping under-voltage and over-voltage transients, the disparity in switching loss between paralleled devices due to propagation delay, a high-frequency oscillatory behavior on gate voltage due to die-to-die interactions, and current equalization in the kelvin-source signal path. In addition, the analysis of parameter variance between paralleled MOSFETs and the effects of mismatched threshold voltage and on-state resistance on switching loss and junction temperature are investigated. Finally, three Miller Clamp topologies are simulated and assessed for effectiveness culminating in a solution for parasitic turn-on in high dv/dt systems such as those utilizing high-performance SiC power modules
