Elastic image registration versus speckle tracking for 2-D myocardial motion estimation: a direct comparison in vivo

Despite the availability of multiple solutions for assessing myocardial strain by ultrasound, little is currently known about the relative performance of the different methods. In this study, we sought to contrast two strain estimation techniques directly (speckle tracking and elastic registration) in an in vivo setting by comparing both to a gold standard reference measurement. In five open-chest sheep instrumented with ultrasonic microcrystals, 2-D images were acquired with a GE Vivid7 ultrasound system. Radial (epsilon(RR)) , longitudinal (epsilon(LL)) , and circumferential strain (epsilon(CC)) were estimated during four inotropic stages: at rest, during esmolol and dobutamine infusion, and during acute ischemia. The correlation of the end-systolic strain values of a well-validated speckle tracking approach and an elastic registration method against sonomicrometry were comparable for epsilon(LL) (r = 0.70 versus r = 0.61, respectively; p = 0.32) and epsilon(CC) (r = 0.73 versus r = 0.80 respectively; p = 0.31). However, the elastic registration method performed considerably better for epsilon(RR) (r = 0.64 versus r = 0.85 respectively; p = 0.09). Moreover, the bias and limits of agreement with respect to the reference strain estimates were statistically significantly smaller in this direction (p < 0.001). This could be related to regularization which is imposed during the motion estimation process as opposed to an a posteriori regularization step in the speckle tracking method. Whether one method outperforms the other in detecting dysfunctional regions remains the topic of future research

Dynamic modeling of pwm and single-switch single-stage power factor correction converters

The concept of averaging has been used extensively in the modeling of power electronic circuits to overcome their inherent time-variant nature. Among various methods, the PWM switch modeling approach is most widely accepted in the study of closed-loop stability and transient response because of its accuracy and simplicity. However, a non-ideal PWM switch model considering conduction losses is not available except for converters operating in continuous conduction mode (CCM) and under small ripple conditions. Modeling of conductor losses under large ripple conditions has not been reported in the open literature, especially when the converter operates in discontinuous conduction mode (DCM). In this dissertation, new models are developed to include conduction losses in the non-ideal PWM switch model under CCM and DCM conditions. The developed model is verified through two converter examples and the effect of conduction losses on the steady state and dynamic responses of the converter is also studied. Another major constraint of the PWM switch modeling approach is that it heavily relies on finding the three-terminal PWM switch. This requirement severely limits its application in modeling single-switch single-stage power factor correction (PFC) converters, where more complex topological structures and switching actions are often encountered. In this work, we developed a new modeling approach which extends the PWM switch concept by identifying the charging and discharging voltages applied to the inductors. The new method can be easily applied to derive large-signal models for a large group of PFC converters and the procedure is elaborated through a specific example. Finally, analytical results regarding harmonic contents and power factors of various PWM converters in PFC applications are also presented here

Universal Digital Controller for Boost CCM Power Factor Correction Stages Based on Current Rebuilding Concept

Continuous conduction mode power factor correction (PFC) without input current measurement is a step forward with respect to previously proposed PFC digital controllers. Inductor volt-second (vsL) measurement in each switching period enables digital estimation of the input current; however, an accurate compensation of the small errors in the measured vsL is required for the estimation to match the actual current. Otherwise, they are accumulated every switching period over the half-line cycle, leading to an appreciable current distortion. A vsL estimation method is proposed, measuring the input (vg) and output voltage (vo). Discontinuous conduction mode (DCM) occurs near input line zero crossings and is detected by measuring the drain-to-source MOSFET voltage vds. Parasitic elements cause a small difference between the estimated voltage across the inductor based on input and output voltage measurements and the actual one, which must be taken into account to estimate the input current in the proposed sensorless PFC digital controller. This paper analyzes the current estimation error caused by errors in the ON-time estimation, voltage measurements, and the parasitic elements. A new digital feedback control with high resolution is also proposed. It cancels the difference between DCM operation time of the real input current, (TDCMg) and the estimated DCM time (TDCMreb). Therefore, the current estimation is calibrated using digital signals during operation in DCM. A fast feedforward coarse time error compensation is carried out with the measured delay of the drive signal, and a fine compensation is achieved with a feedback loop that matches the estimated and real DCM time. The digital controller can be used in universal applications due to the ability of the DCM time feedback loop to autotune based on the operation conditions (power level, input voltage, output v- ltage...), which improves the operation range in comparison with previous solutions. Experimental results are shown for a 1-kW boost PFC converter over a wide power and voltage range

Current error compensation for current-sensorless power factor corrector stage in continuous conduction mode

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. V. M. Lopez-Martin, F. J. Azcondo, and A. de Castro, "Current error compensation for current-sensorless power factor corrector stage in continuous conduction mode", 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL), Kyoto (Japan), 2012, pp. 1-8A universal digital PFC current-sensorless controller based on control of estimated current is presented. Parasitic elements cause a small difference between the measured input voltage and the voltage across the inductance in a boost converter, which must be taken into account to estimate the input current in a sensorless PFC digital controller. To compensate for the deviation caused by the parasitic elements, and so minimize the current estimation error, the article proposes a digital feedback control technique that cancels the time difference between DCM operation time of the real input current (TinDCM) and the estimated current (TrebDCM). Experimental results, obtained using a boost PFC converter under different conditions, are shown for verification purposes.This work was supported by the Spanish Ministry of Science TEC FEDER 2011-2361

Bridgeless SEPIC Converter Based Computer Power Supply Using Coupled Inductor

Switched Mode Power Supplies (SMPS) are used as power source for computers. Conventional SMPS used in computers are suffered by some serious problems such as poor power quality, high device stress, slow dynamic response, high harmonic contents, periodically dense, peak currents, distorted input current. To minimize these problems, a non-isolated bridgeless buck-boost single ended primary inductance converter (SEPIC) using coupled inductor is introduced at the front end of the SMPS, which is operated in discontinuous conduction mode (DCM). This proposed technique reduces the Total Harmonic Distortion(THD), which results in power factor improvement. The DC output voltage of the SMPS is almost a constant voltage which is regulated by means of the proposed SEPIC converter. For obtaining different dc voltage levels for the PC applications, the output of the front end SEPIC converter is fed to the half-bridge DC-DC converter. The output voltages of the SMPS are controlled by controlling any one of the output voltages. Design and simulation of the proposed converter are carried out using the MATLAB/simulink software