Emulation of Circuits under Test Using Low-Cost Embedded Platforms

Electrical engineering education requires the development of the specific ability and skills to address the design and assembly of practical electronic circuits, as well as the use of advanced electronic instrumentation. However, for electronic instrumentation courses or any other related specialty that pursues to gain expertise testing a physical system, the circuit assembly process itself can represent a bottleneck in a practical session. The time dedicated to the circuit assembly is subtracted both to the measurements and the final decision-making time. Therefore, the student's practical experience is limited. This article presents a reconfigurable physical system based on the Arduino (TM) shield pin-out, which (after specific programming) can virtually behave as a device under test to carry out measurement procedures on it, emulating any system or process. Although it has been mainly oriented to the Arduino boards, it is possible to add different control devices with a connector compatible. The user does not need to assemble any circuit. Our approach does not only pursue the correct instrument handling as a goal, but it also immerses the student in the context of the functional theory of the proposed circuit under test. Consequently, the same emulation platform can be utilized for other techno-scientific specialties, such as electrical engineering, automatic control systems or physics courses. Besides that, it is a compact product that can be adapted to the needs of any teaching institution.This work was performed as an innovation and teaching improvement project and supported by grant SOL-201700083174-TRA from Vicerrectorado de Recursos Docentes y de la Comunicacion, University of Cadiz

CABE : a cloud-based acoustic beamforming emulator for FPGA-based sound source localization

Microphone arrays are gaining in popularity thanks to the availability of low-cost microphones. Applications including sonar, binaural hearing aid devices, acoustic indoor localization techniques and speech recognition are proposed by several research groups and companies. In most of the available implementations, the microphones utilized are assumed to offer an ideal response in a given frequency domain. Several toolboxes and software can be used to obtain a theoretical response of a microphone array with a given beamforming algorithm. However, a tool facilitating the design of a microphone array taking into account the non-ideal characteristics could not be found. Moreover, generating packages facilitating the implementation on Field Programmable Gate Arrays has, to our knowledge, not been carried out yet. Visualizing the responses in 2D and 3D also poses an engineering challenge. To alleviate these shortcomings, a scalable Cloud-based Acoustic Beamforming Emulator (CABE) is proposed. The non-ideal characteristics of microphones are considered during the computations and results are validated with acoustic data captured from microphones. It is also possible to generate hardware description language packages containing delay tables facilitating the implementation of Delay-and-Sum beamformers in embedded hardware. Truncation error analysis can also be carried out for fixed-point signal processing. The effects of disabling a given group of microphones within the microphone array can also be calculated. Results and packages can be visualized with a dedicated client application. Users can create and configure several parameters of an emulation, including sound source placement, the shape of the microphone array and the required signal processing flow. Depending on the user configuration, 2D and 3D graphs showing the beamforming results, waterfall diagrams and performance metrics can be generated by the client application. The emulations are also validated with captured data from existing microphone arrays.</jats:p

Analog Reconfigurable Circuits

The aim of this paper is to present an overview of a new branch of analog electronics represented by analog reconfigurable circuits. The reconfiguration of analog circuits has been known and used since the beginnings of electronics, but the universal reconfigurable circuits called Field Programmable Analog Arrays (FPAA) have been developed over the last two decades. This paper presents the classification of analog circuit reconfiguration, examples of FPAA solutions obtained as academic projects and commercially available ones, as well as some application examples of the dynamic reconfiguration of FPAA.

Exploiting partial reconfiguration through PCIe for a microphone array network emulator

The current Microelectromechanical Systems (MEMS) technology enables the deployment of relatively low-cost wireless sensor networks composed of MEMS microphone arrays for accurate sound source localization. However, the evaluation and the selection of the most accurate and power-efficient network’s topology are not trivial when considering dynamic MEMS microphone arrays. Although software simulators are usually considered, they consist of high-computational intensive tasks, which require hours to days to be completed. In this paper, we present an FPGA-based platform to emulate a network of microphone arrays. Our platform provides a controlled simulated acoustic environment, able to evaluate the impact of different network configurations such as the number of microphones per array, the network’s topology, or the used detection method. Data fusion techniques, combining the data collected by each node, are used in this platform. The platform is designed to exploit the FPGA’s partial reconfiguration feature to increase the flexibility of the network emulator as well as to increase performance thanks to the use of the PCI-express high-bandwidth interface. On the one hand, the network emulator presents a higher flexibility by partially reconfiguring the nodes’ architecture in runtime. On the other hand, a set of strategies and heuristics to properly use partial reconfiguration allows the acceleration of the emulation by exploiting the execution parallelism. Several experiments are presented to demonstrate some of the capabilities of our platform and the benefits of using partial reconfiguration

FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration

In this paper, the implementation on a Field Programmable Gate Array (FPGA) of Relaxation Digital to Analog Converters (ReDACs), which take advantage of the impulse response of a first-order RC network to generate and combine binary weighted voltages, is addressed. For this purpose, the dominant ReDAC nonlinearity limitation related to the parasitics of the RC network is analyzed and a simple and robust technique for its effective suppression is proposed. Moreover, a ReDAC foreground digital calibration strategy suitable to FPGA implementation is introduced to tune the clock frequency of the converter, as requested for ReDAC operation. The novel error suppression technique and calibration strategy are finally implemented on a 13-bit, 514,S/s prototype (ReDAC1) and on a 11-bit, 10.5,kS/s prototype (ReDAC2), which are experimentally characterized under static and dynamic conditions. Measured results on ReDAC1 (ReDAC2) reveal 1.68,LSB (1.53,LSB) maximum INL, 1.54,LSB (1.0,LSB) maximum DNL, 76.4,dB (67.9,dB) THD, 79.7,dB (71.4,dB) SFDR and 71.3,dB (63.3,dB) SNDR, corresponding to 11.6 (10.2) effective bits (ENOB)

Real-time digital signal processing system for normal probe diffraction technique

Ultrasonic systems are widely used in many fields of non-destructive testing. The increasing requirement for high quality steel product stirs the improvement of both ultrasonic instruments and testing methods. The thesis indicates the basics of ultrasonic testing and Digital Signal Processing (DSP) technology for the development of an ultrasonic system. The aim of this project was to apply a new ultrasonic testing method - the Normal Probe Diffraction method to course grained steel in real-time and investigate whether the potential of probability of detection (POD) has been improved. The theories and corresponding experiment set-up of pulse-echo method, TOFD and NPD method are explained and demonstrated separately. A comparison of these methods shows different contributions made by these methods using different types of algorithms and signals. Non-real-time experiments were carried out on a VI calibration block using an USPC 3100 ultrasonic testing card to implement pulse-echo and NPD method respectively. The experiments and algorithm were simulated and demonstrated in Matlab. A low frequency Single-transmitter-multi-receiver ultrasonic system was designed and built with a digital development board and an analogue daughter card to transmit or receive signals asynchronously. A high frequency high voltage amplifier was designed to drive the ultrasonic probes. A Matlab simulation system built with Simulink indicates that the Signal to Noise Ratio (SNR) can be improved with an increment of up to 3dB theoretically based on the simulation results using DSP techniques. The DSP system hardware and software was investigated and a real-time DSP hardware system was supposed to be built to implement the high frequency system using a rapid code generated system based on Matlab Simulink model and the method was presented. However, extra effort needs to be taken to program the hardware using a low-level computer language to make the system work stably and efficiently

Interfacing of neuromorphic vision, auditory and olfactory sensors with digital neuromorphic circuits

The conventional Von Neumann architecture imposes strict constraints on the development of intelligent adaptive systems. The requirements of substantial computing power to process and analyse complex data make such an approach impractical to be used in implementing smart systems. Neuromorphic engineering has produced promising results in applications such as electronic sensing, networking architectures and complex data processing. This interdisciplinary field takes inspiration from neurobiological architecture and emulates these characteristics using analogue Very Large Scale Integration (VLSI). The unconventional approach of exploiting the non-linear current characteristics of transistors has aided in the development of low-power adaptive systems that can be implemented in intelligent systems. The neuromorphic approach is widely applied in electronic sensing, particularly in vision, auditory, tactile and olfactory sensors. While conventional sensors generate a huge amount of redundant output data, neuromorphic sensors implement the biological concept of spike-based output to generate sparse output data that corresponds to a certain sensing event. The operation principle applied in these sensors supports reduced power consumption with operating efficiency comparable to conventional sensors. Although neuromorphic sensors such as Dynamic Vision Sensor (DVS), Dynamic and Active pixel Vision Sensor (DAVIS) and AEREAR2 are steadily expanding their scope of application in real-world systems, the lack of spike-based data processing algorithms and complex interfacing methods restricts its applications in low-cost standalone autonomous systems. This research addresses the issue of interfacing between neuromorphic sensors and digital neuromorphic circuits. Current interfacing methods of these sensors are dependent on computers for output data processing. This approach restricts the portability of these sensors, limits their application in a standalone system and increases the overall cost of such systems. The proposed methodology simplifies the interfacing of these sensors with digital neuromorphic processors by utilizing AER communication protocols and neuromorphic hardware developed under the Convolution AER Vision Architecture for Real-time (CAVIAR) project. The proposed interface is simulated using a JAVA model that emulates a typical spikebased output of a neuromorphic sensor, in this case an olfactory sensor, and functions that process this data based on supervised learning. The successful implementation of this simulation suggests that the methodology is a practical solution and can be implemented in hardware. The JAVA simulation is compared to a similar model developed in Nengo, a standard large-scale neural simulation tool. The successful completion of this research contributes towards expanding the scope of application of neuromorphic sensors in standalone intelligent systems. The easy interfacing method proposed in this thesis promotes the portability of these sensors by eliminating the dependency on computers for output data processing. The inclusion of neuromorphic Field Programmable Gate Array (FPGA) board allows reconfiguration and deployment of learning algorithms to implement adaptable systems. These low-power systems can be widely applied in biosecurity and environmental monitoring. With this thesis, we suggest directions for future research in neuromorphic standalone systems based on neuromorphic olfaction

Emulation of Narrowband Powerline Data Transmission Channels and Evaluation of PLC Systems

This work proposes advanced emulation of the physical layer behavior of NB-PLC channels and the application of a channel emulator for the evaluation of NB-PLC systems. In addition, test procedures and reference channels are proposed to improve efficiency and accuracy in the system evaluation and classification. This work shows that the channel emulator-based solution opens new ways toward flexible, reliable and technology-independent performance assessment of PLC modems

Component-Level Electronic-Assembly Repair (CLEAR) Synthetic Instrument Capabilities Assessment and Test Report

The role of synthetic instruments (SIs) for Component-Level Electronic-Assembly Repair (CLEAR) is to provide an external lower-level diagnostic and functional test capability beyond the built-in-test capabilities of spacecraft electronics. Built-in diagnostics can report faults and symptoms, but isolating the root cause and performing corrective action requires specialized instruments. Often a fault can be revealed by emulating the operation of external hardware. This implies complex hardware that is too massive to be accommodated in spacecraft. The SI strategy is aimed at minimizing complexity and mass by employing highly reconfigurable instruments that perform diagnostics and emulate external functions. In effect, SI can synthesize an instrument on demand. The SI architecture section of this document summarizes the result of a recent program diagnostic and test needs assessment based on the International Space Station. The SI architecture addresses operational issues such as minimizing crew time and crew skill level, and the SI data transactions between the crew and supporting ground engineering searching for the root cause and formulating corrective actions. SI technology is described within a teleoperations framework. The remaining sections describe a lab demonstration intended to show that a single SI circuit could synthesize an instrument in hardware and subsequently clear the hardware and synthesize a completely different instrument on demand. An analysis of the capabilities and limitations of commercially available SI hardware and programming tools is included. Future work in SI technology is also described

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements